Fast initialization of GPIO for 4412 Development Board Linux-driven tutorials

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The initialization of the GPIO

? Using the command "LS drivers/gpio/*.o" in the kernel source directory, you can see that "Gpio-exynos4" is compiled into the kernel

– Generate the. o File represents the final compilation into the kernel

– In addition to the Menuconfig configuration file, the. o file can also be used to determine whether the file is compiled into a

Kernel

? In the bottom line of the "gpio-exynos4.c" file

–core_initcall (Exynos4_gpiolib_init);

The –core_initcall represents a call during the initialization of Linux

– The initialization function is defined in the "include/linux/init.h" file in the source directory, and the header file

A series of initialization functions are defined in the Linux boot process, which is rated as

Structural Body Exynos4_gpio_common_4bit

? Taking a structure with label= "GPL2" as an example

? . Base = (S5p_va_gpio2 + 0x100)

– Represents an offset address and a virtual address addition

? . Eint_offset = 0x20

– Represents the interrupt section, when the interrupt is introduced (IO Port can be configured as interrupt mode)

? . Group =

– To Group GPIO

? chip.base = exynos4_gpl2 (0),

– Macro definition exynos4_gpl2 (0) assignment to initialization function

? Chip.ngpio = Exynos4_gpio_l2_nr

– Indicates that there are several GPIO in this group

? Chip.label = "GPL2",

– A sign that programmers need to care about

? Macro definition exynos4_gpl2 (0) analysis

– Exynos4_gpl2 (_NR) (Exynos4_gpio_l2_start + (_NR))

– Enumerating GPIO

– exynos4_gpio_l2_start= Exynos4_gpio_next (EXYNOS4_GPIO_L1)

– exynos4_gpio_next macro definition

– #define EXYNOS4_GPIO_NEXT (__gpio) \ ((__gpio# #_START) + (__gpio# #_NR)

+ config_s3c_gpio_space + 1)

? GPIO the number EXYNOS4_GPIO_L2_NR

– can be found through the manual

? S5p_va_gpio2

– Virtual Address

? Looking for the S5p_va_gpio2 macro definition, you can see that all GPIO is divided into 4 Banks , which

The datasheet and the upper one are consistent.

– S5p_va_gpio1

– S5p_va_gpio2 s3c_addr (0x02240000)

– S5p_va_gpio3

– S5p_va_gpio4

? Find the s3c_addr macro definition

– #define S3C_ADDR (x) (S3c_addr_base + (x) )

? Find the s3c_addr_base macro definition, which is a virtual address, as you can see, the address

Range exceeding 1G or 2G of memory

– #define S3c_addr_base 0xf6000000

Mapping relationships between physical addresses and virtual addresses

? Virtual address and Physical address mapping

– Virtual address is generally good to find, generally in the platform-related gpio files can be found in the macro definition

? Search for the keyword "s5p_va_gpio2" in source Insight and see where it's used

Macro definition. The search time will be longer,1-5 minutes.

? After searching, you can see that in addition to the gpio-exynos4.c file,Cpu-exynos

Also used in the, this is a platform file

? The map array as shown in

? Explanation of structural Body

- . Virtual = (unsigned long) S5p_va_gpio2, which represents the virtual address

– . PFN = __PHYS_TO_PFN (Exynos4_pa_gpio2), which represents the physical Address

– . Length = sz_4k, which indicates the width of the map

– . Type = Mt_device,

? Find a macro definition Exynos4_pa_gpio2

– #define Exynos4_pa_gpio2 0x11000000

– This physical address 0x11000000 is

the initialization process of GPIO

? A simple description of the initialization process

– The platform file defines the physical address and the virtual address, respectively.

– Mapping between physical address and virtual address

? In initialization, a GPIO macro definition that the programmer needs to use is introduced , and the macro definition is loaded into the

in the chip structure

the calling function of the GPIO

? For example , the s3c_gpio_cfgpin function in the header file gpio-cfg.h . This function is for a GPIO.

The first parameter is the macro exynos4_gpl2 (0)and the second is the configured state parameter

– Configuration header file in arm/arm/plat-samsung/include/plat/gpio-cfg.h

? To find the function, you can see that the entry function calls the chip structure

– s3c_gpiolib_getchip, after the function is called by the pin , returns the s3c_gpios[chip]

Parameters

– exynos4_gpio_common_4bit[] and S3c_gpios are both structural bodies s3c_gpio_chip type of

Data

– then calculate the offset address and a series of operations, which are the Linux kernel and the Samsung platform end

The details are not to be managed.

? When we control Gpio , we can use Some of the GPIO's processing functions to add similar

EXYNOS4_GPL2 (0) macro definition, you can operate GPIO

? The use of common functions in the GPIO operation is described in detail later

Problems

? Not a good paging size to be the same, how GPIO through the MMU processing, there are

sz_256 and sz_4k?

– in fact , when the CPU looks for an address, it still passes through memory. the MMU itself does not save the exact number

The main is to provide a virtual address and physical address of the table, the table also has a field of long

Degree. This paging has nothing to do with the MMU , it's CPU Memory and communication between physical addresses .

The concept. This is just an abstract concept, understanding the MMU is just a table,CPU to GPIO

The operation is very well understood.

? The internal register is not very fast, why does theCPU not read directly?

– The internal registers are very fast, but they are very slow relative to the CPU . CPU processing data is the memory

In a large segment of a large segment processing, if a single read the value of the internal register, the CPU is extremely

Waste. The internal register is also considered a "special physical Address".

? Only the virtual address and physical address corresponding array, why did not introduce where the call?

– You can take a look at the function ioremap, whichLinux calls this function to implement the gpio mapping off

System

– It's enough to go deeper today, so if you can just understand the meaning of the story.

, this thing to our actual write-driven help is not so big!

? If I still can't understand it. The operation of the macro definition exynos4_gpl2 (0) is the 4412 Core

Chip pin AC21 Register Operation ", how to do?

– Remember this conclusion to be able to set the macro variable exynos4_gpl2 (0) and the GPL of this group of GPIO 0 bit

Register associative.

– Follow me to the gourd painting scoop, do not affect the actual writing procedures, interested in back to understand

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The initialization of Gpio for the 4412 board Linux driver tutorial