Follow Mr. Wei to learn Linux learning Notes (ii)-Storage Manager

(1) Basic principle diagram of CPU operating peripherals

The graph shows that the CPU wants to access a peripheral, which is implemented through the storage Manager. In this paper, the main operation of SDRAM to implement Storage Manager learning.

(2), Configuration principles and procedures

To access the configuration information required for a chip:

1. Chip selection Signal

2. Address Line

3, data line, even if the data width

4, clock \ Frequency

5, chip-related things: for SDRAM

A) How many digits are there in the line address

b) How many digits are there in the column address

c) How many bits are there in the bank

The steps to operate an SDRAM are:

A, first select the SDRAM by the chip selection signal

b, and then determine which Bnak is stored inside

C, then issue the line address, in the issue column address, determine the data location in SDRAM

(3), hardware-related information

SDRAM schematic diagram

SDRAM Chip Brochure

2440 Storage Controller Manual

The configuration data for SDRAM is shown by viewing the schematic and data sheets as follows:

A, the data bit width 32 bits, because uses 2 pieces of SDRAM, a piece is 16 bits.

B, row 13-bit, column 9-bit, by the figure SDRAM Chip handbook.

C, Refresh cycle 64ms/8192

D, the bank has 4 bits, the storage controller Manual of Figure 2440 shows that the bank address is a[25:24],.

View 2440 The manual indicates that the SDRAM hardware connection is allocated as

The address of SDRAM is from Addr2~addr14, without ADDR0 and ADDR1, because our memory access is 32-bit access, each read and write is 4 bytes, which causes the address ADDR0 and ADDR1 representatives of the address 0, 1, 2 and 3 are unable to be read by a single, Each time the addresses 0, 1, 2, and 3 are read with a 32-bit data, so the address line ADDR0 and ADDR1 are ignored, and the address line is addr2~addr14.

2440 There are 8 banks that can connect 8 SDRAM-like peripherals. And our SDRAM connected to the BANK6 above, the starting address is 0x30000000, our SDRAM is 64MB, so the access space is 0x30000000~0x33ffffff.

(4), program code

1 . equ mem_ctl_base, 0x48000000 @ because the start address of the storage controller is 0x480000002 . equ sdram_base, 0x30000000 @ as on the initial access address of SDRAM is 0x300000003 . Text4 . Global _start5 _start:6 BL Disable_watch_dog @ off watchdog, otherwise the CPU will continue to restart7 BL Memsetup @ set up storage controller8 bl copy_steppingstone_to_sdram @ copy code into SDRAM9 Ldr pc, =on_sdram @ jump to SDRAM continue executionTen On_sdram: One Ldr sp, =0x34000000 @ sets the stack, because the program is copied to the SDRAM inside the run, the stack space is set to the first 4k content of SDRAM.  A BL main - Halt_loop: - b halt_loop the  - Disable_watch_dog: - @ Go to watchdog register write 0 -     movR1, #0x53000000 +     movR2, #0x0 -     StrR2, [R1] +     movpc, LR @ back A  at Copy_steppingstone_to_sdram: - @ Copy all Steppingstone 4K data into SDRAM - @ steppingstone Start address is 0x00000000,sdram with start address 0x30000000 -      -     movR1, #0 - LDR R2, =sdram_base in     movR3, #4*1024x768 - 1:   toLDR R4, [r1],#4@ Read 4 bytes of data from Steppingstone and let the source address add 4 +     StrR4, [r2],#4@ Copy this 4 bytes of data into the SDRAM and let the address of the target add 4 -     CMPR1, R3 @ To determine whether to complete: the source address is equal to the steppingstone address?  the BNE 1b @ if not finished, continue *     movpc, LR @ back $ Panax Notoginseng Memsetup: - @ set up the storage controller to use peripherals such as SDRAM the  +     movR1, #MEM_CTL_BASE the start address of 13 registers of the storage controller A ADRL R2, Mem_cfg_val @ The starting storage address for these 13 values the     AddR3, R1, # the@ -*4= Wu + 1:   -LDR R4, [R2], #4@ Read the set value and let R2 add 4 $     StrR4, [R1], #4@ Write this value to register and let R1 add 4 $     CMPR1, R3 @ determine if all 13 registers are set - BNE 1b @ if not written, continue -     movpc, LR @ back the  - Wuyi. align4 the Mem_cfg_val: - @ Storage Controller 13 registers set value Wu . Long 0x22011110 @ Bwscon - . Long 0x00000700 @ BANKCON0 About . Long 0x00000700 @ BANKCON1 $ . Long 0x00000700 @ BANKCON2 - . Long 0x00000700 @ BANKCON3 - . Long 0x00000700 @ BANKCON4 - . Long 0x00000700 @ BANKCON5 A . Long 0x00018005 @ BANKCON6 + . Long 0x00018005 @ BANKCON7 the . Long 0X008C07A3 @ REFRESH - . Long 0x000000b1 @ banksize $ . Long 0x00000030 @ MRSRB6 the. Long 0x00000030 @ MRSRB7

The main difference between the program and the previous one is to add the copy code to the SDRAM program.

Because the program is finally executed in SDRAM, we set the code starting segment address to 0x30000000 in makefile.

1 arm-linux-ld-ttext 0x30000000 head.o leds.o-o sdram_elf

The procedure is executed in the following process:

First the program starts from Nandflash, and the first 4K content copy fragments inside RAM, then the program executes, first shuts down the watchdog, sets the SDRAM related register, initializes the SDRAM.

After the SDRAM initialization completes, starts executes the Copy_steppingstone_to_sdram program, this program is copies our program to the SDRAM inside executes, the copy completes the program the starting address becomes the 0x3000000. and set the 4k stack space.

Follow Mr. Wei to learn Linux learning Notes (ii)-Storage Manager