LCD knowledge points and LCD knowledge points

LCD knowledge points and LCD knowledge points

1. LCD is a liquid crystal display. The control principle is to control the electron gun in the LCD. Different colors are projected on the screen of n rows * n columns to form an image.

 

2. programming steps:

① Enable LCD Backlight
Set the GPIO corresponding to the LCD backlight to prohibit pulling (GPxUP corresponding bit write 1), select the output type (GPxCON corresponding bit write 01 ), output is high (GPxDAT corresponding bit write 1 ).

② Enable LCD Power Supply
GPG4 can be selected as LCD _PWREN (GPGCON: 9-8 write 11). At this time, the LCD power can be switched on/off through LCDCON5: 3.
You can also customize other GPIO as the LCD power switch. You only need to set this GPIO to prohibit pulling (GPxUP corresponding bit write 1) and select the output type (GPxCON corresponding bit write 01 ), the output is a high level (GPxDAT corresponding bit write 1) to turn on the LCD power.

③ Set other signal lines
Other signal lines include VD0-VD23, VFRAME, VLINE, VCLK, etc., respectively in GPCCON, GPDCON select the corresponding function.

④ Set the LCD frequency (VCLK)
The Datasheet of the LCD usually shows a recommendation frequency. For example, if the recommended frequency of the screen I use is 6.4 MB, I need to select a suitable CLKVAL through some calculations to generate this frequency:
For tft LCD, the formula for calculating the VCLK provided by S3C2440 is:
VCLK = HCLK/(CLKVAL + 1) * 2)
We can conclude that:
CLKVAL = HCLK/(VCLK * 2)-1
My HCLK is 100 Mhz (CPU runs at 400 Mhz, CLKDIV_VAL is set to 5, Fclk: Hclk: Pclk =), and VCLK uses the 6.4 M recommended on the screen:
CLKVAL = 100000000/(6400000*2)-1 = 6.8
Select the nearest integer 7 and write it into LCDCON1: 17-8.
(VCLK is actually calculated based on the number of frames per second * Number of frames * row pixels. The number of frames and row pixels must contain the number of spaces and the number of the same step)

⑤ Set other related parameters
LCD parameters mainly include the following:
LINEVAL: LCD horizontal pixel-1, such as 320-1 = 319
HOZVAL: LCD vertical pixel-1, such as 240-1 = 239
HFPD: Number of VCLK clock before the start of the line (Datasheet on the LCD screen is generally recommended)
HBPD: Number of VCLK clock after the end of the row (Datasheet on the LCD screen generally has a recommended value)
HSPW: Number of invalid VCLK clock for Horizontal synchronization between rows (Datasheet on the LCD screen is generally recommended)
VFPD: Number of blank lines before the start of frame data (Datasheet on the LCD screen is generally recommended)
VBPD: Number of blank lines after the frame data ends (Datasheet on the LCD screen generally has a recommended value)
VSPW: Invalid Number of lines for Vertical synchronization between frames (Datasheet on the LCD screen is generally recommended)
(Related registers: LCDCON2, LCDCON3, and LCDCON4)

⑥ Set the video buffer address
2440 supports Virtual screens and enables rapid screen movement by changing LCD registers
PAGEWIDTH: the number of bytes of a row on the virtual screen. If you do not use the virtual screen, set it to the number of bytes of the row on the actual screen. For example, if the 16-Bit Width is 320 pixels, set it to 320*2.
OFFSIZE: the number of bytes at the left offset of the virtual screen. If the virtual screen is not used, set it to 0.
LCDBANK: Video Frame Buffer Memory Address 30-22 Bits
LCDBASEU: the starting address of the video frame buffer, Which is 21-1.
LCDBASEL: the end address of the video frame buffer, Which is 21-1.
(Related registers: LCDSADDR1, LCDSADDR2, and LCDSADDR3)

7. Determine the polarity of the signal
The LCD controller of 2440 allows you to set the polarity of signals such as VCLK, VLINE, and VFRAME (the rising edge is valid or the falling edge is valid), which must be determined one by one against the Datasheet of the LCD.
(Related registers LCDCON5)

⑧ Disable the LPC3600/LCC3600 mode!
If you do not use Samsung LPC3600/LCC3600 LCD, you must disable the LPC3600/LCC3600 mode (write 0 to TCONSEL )!

⑨ Enable video output
ENVID is set to 1 (LCDCON1: 0 write 1)

 

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4.

A: The display pointer starts from the first point of the first line in the upper left corner of the rectangle. A point and A point are displayed on the LCD. In the time sequence diagram above, the time series are represented as VCLK, we call it a pixel clock signal;
B: When the display pointer is always displayed to the right of the rectangle and the row ends, the action of this row is called 1 Line in the above sequence diagram;
C: the pointer is displayed again on the left of the rectangle and starts from the second line. Note that it takes some time to display the pointer back to the left of the second line from the right of the first line, we call it row switching;
D: Similarly, the display pointer is displayed in the lower right corner of the rectangle only when a row is displayed. Therefore, the display of this row on the time line is the HSYNC in the time sequence diagram.

E: However, the LCD display is not a quick display of a pair of images. for continuous and stable display on the LCD, you need to switch to another image (the other image can be the same or different from the previous image, just to display the image continuously on the LCD ). Therefore, this image is called a Frame, which is expressed as a Frame in the sequence diagram. Therefore, from the sequence diagram, we can see that 1 Line is only one row in 1 Frame;
F: Similarly, frame switching also takes some time. We call it frame switching. The entire LCD display process is displayed on the timeline, it can be expressed as VSYNC on the sequence chart.