[SPI&I2C] Introduction to I²C and SPI protocols

IICVs SPI

Today, in low-end digital communications applications, we are seen in IIC (inter-integrated circuit) and SPI (Serial peripheral Interface). The reason is that these two communication protocols are ideal for near- low-speed inter-chip communication. Philips (for IIC) and Motorola (for SPI) have developed both standard communication protocols for different backgrounds and market requirements.

IIC was developed in 1982 to provide a simpler way to interconnect the CPU and peripheral chips in the TV set. Television is one of the earliest embedded systems, and the initial embedded system uses memory mapping (memory-mapped I/O) to interconnect microcontrollers and peripherals. To implement memory mapping, the device must parallel the data and address lines of the microcontroller, which requires a large number of lines and additional address decoding chips when connecting multiple peripherals, which is inconvenient and costly.

To conserve the microcontroller's pins and additional logic chips, making the printed circuit board simpler and cheaper, the Philips laboratory in the Netherlands developed the ' inter-integrated circuit ', IIC or IIC, a bus protocol that uses only two wires to connect all peripheral chips. The initial standard defines a bus speed of 100kbps. Several revisions have been experienced, mainly in the 1995 400kbps,1998 3.4Mbps.

There are indications that the SPI bus was first introduced in 1979, when Motorola integrated the SPI bus on their first microcontroller chip, which was switched from 68000 microprocessors. The SPI bus is the external bus for the microcontroller four-wire (relative to the internal bus). Unlike IIC, SPI has no clear-text standard, it is only a fact standard , the implementation of communication operations only as a general abstract description, chip manufacturers and driver developers through the data sheets and application notes communication implementation details.

SPI

For experienced digital electronics engineers, it is quite straightforward to interconnect two digital devices with the SPI. SPI is a four signal line protocol ():

§sclk:serial Clock (output from master);

§mosi; Simo:master output, Slave Input (output from Master);

§miso; Somi:master Input, Slave output (output from Slave);

§ss:slave Select (Active low, Outputfrom master).

The SPI is a [ single-Master device (Single-master)] communication protocol, which means that only one central device in the bus can initiate communication. when the SPI master device wants to read/write [slave device], it first pulls down [from the device] corresponding to the SS line (the SS is active low), and then began to send the work pulse to the clock line, the corresponding pulse time, [main device] sends the signal to the MOSI implementation " write ", " Read " can also be achieved for miso sampling, such as:

SPI has four modes of operation- mode 0, Mode 1, Mode 2 and Mode 3, the difference is defined in the clock pulse which edge conversion (toggles) output signal, which edge sampling input signal, There is also a steady-level value for the clock pulse (which is high or low when the clock signal is invalid). Each pattern is characterized by a pair of parameters, which are called clock polarity cpol and clock phase cpha.

[Master and slave devices] must use the same operating parameters--SCLK, Cpol, and cpha to work properly. If there are multiple [slave devices], and they use different working parameters, the [master] must reconfigure These parameters between read and write different [from device]. The main content of the SPI bus protocol above. SPI does not specify the maximum transfer rate, no address scheme, and the SPI does not specify a communication response mechanism, there is no rules for flow control.

In fact, the spi[master device] does not even know whether the specified [slave device] exists. These communication controls have to be implemented by themselves outside the SPI protocol. For example, to connect a [command-response-control] decoding chip with an SPI, a more advanced communication protocol must be implemented on the basis of the SPI. The SPI does not care about the electrical characteristics of the physical interface, such as the standard voltage of the signal. At first, most SPI applications used intermittent clock pulses and transmitted data in bytes, but now there are many variants that implement continuous-time pulses and arbitrary-length data frames.

IIC

Unlike SPI's single-master device, IIC is a multi-master bus, IIC does not have a physical chip selection signal line, no quorum logic circuit, only two signal lines are used-' serial data ' (SDA) and ' Serial Clock ' (SCL). The IIC agreement stipulates that:

§ First, each IIC equipment has a unique seven-bit device address;

§ Second, the data frame size is 8 bits of bytes;

§ Third, some data bits in the data (frame) are used to control the start, stop, direction (read-write), and response mechanisms of the communication.

IIC data transfer rates are in standard mode (at 1 Kbps), in fast mode (up to Kbps), and in high-speed mode (3.4 Mbps), while some variants implement low-speed mode (up to ten Kbps) and fast + mode (at a rate of up to two Mbps).

On the physical realization, the IIC bus consists of two signal lines and a ground wire. Two signal lines are two-way transmission, reference. The IIC protocol standard specifies that the device initiating the communication is called the primary device, and that after the primary device initiates one communication, the other devices are slave devices.

The IIC communication process is probably as follows . first , the main device sends a start signal, which is like shouting to all other devices: please pay attention! Other devices then start listening to the bus to prepare to receive the data. next , the main device sends a 7-bit device address plus a read-write operation of the data frame. When the device receives the data, the target device is compared to the address itself. If the match is not true, the device enters the waiting state, waits for the stop signal to arrive, and if the match is matched , the device sends a response signal--acknowledge.

When the main device receives an answer, it starts transmitting or receiving data. The data frame size is 8 bits, followed by a one-bit response signal. The main device sends the data, answers from the device, and the master device answers the data. When the data transfer is complete, the main device sends a stop signal to the other devices to release the bus, the other devices back to the initial state.

Based on the physical structure of the IIC bus, the start and stop signals on the bus must be unique . In addition, the IIC Bus standard stipulates that the data conversion of the SDA line must be at the low level of the SCL line, and the data on the SDA line is stable at the high level of the SCL line.

On the physical implementation, both the SCL and SDA lines are open-drain (open-drain), with a pull-up resistor plus a voltage source. When the line is grounded, the line is logic 0, when the line is released and the line is idle, the line is logic 1. Based on these characteristics, the IIC device operates on the bus only "grounding the line"-Output logic 0.

The IIC bus design uses only two lines, but it is perfectly elegant to achieve seamless communication between any number of devices. Let's imagine what would happen if two devices were sending information to the SCL and SDA lines at the same time.

Based on the design of IIC bus, there is no possibility of level conflict on the line. If a device sends logic 0, the other sends logic 1, then the line sees only logic 0. In other words, if there is a level conflict, sending logic 0 is always "winner".

The physical structure of the bus also allows the main device to read data while writing data to the bus. This way, any device can detect the occurrence of a conflict. When two main devices compete for the bus, the "winner" is unaware of the competition, and only The "loser" discovers the conflict--when it writes a logic 1, but reads 0 o'clock--and exits the competition.

10-bit device address

Any IIC device has a 7-bit address, in theory, there are only 127 different IIC devices in reality. In fact, there are already more types of IIC equipment than this limit, the probability of the same address on a bus for the IIC equipment is quite high. to break this limit, many devices use a dual address -7-bit address plus pin address (external configuration pins). The IIC standard also predicts this limitation, proposing a 10-bit address scheme.

The 10-bit address scheme has a two-point impact on the IIC protocol:

§ First, the address frame is two bytes long, the original is a byte;

§ Second, the first byte, the top five most significant bit, is used as the 10-bit address identifier, and the contract is "11110".

In addition to the 10-bit address identification, the standard also reserved some address codes for other purposes, such as the following table:

Clock Stretching

In IIC communication, the master device determines the clock speed. Because the clock pulse signal is explicitly emitted by the main device. However, when the device is not able to keep up with the speed of the main device, a mechanism is required from the device to request the main device to slow down. This mechanism is called clock stretching, and the mechanism is realized based on the particularity of the I²C structure. When the device needs to reduce the speed of transmission, it can press the clock line, forcing the main device to enter the waiting state, until the clock line from the device to release the communication to continue.

High Speed mode

In principle, using a pull-up resistor to set logic 1 limits the maximum transmission speed of the bus. And speed is one of the factors restricting bus application. This also explains why high-speed mode (3.4 Mbps) is introduced. Before initiating a high-speed mode transfer, the primary device must first emit a specific "Hi speed Master" signal in slow mode (for example, quick mode). To shorten the signal cycle and increase the bus speed, the high-speed mode must use an additional I/O buffer. In addition, the bus quorum can be shielded in high-speed mode. For more information, please participate in the bus standard documentation.

IIC vs SPI: Who is the winner?

Let's compare some of the key points of the IIC and SPI:

first, bus topology/signal routing/hardware resource cost

IIC requires only two signal lines, while the standard SPI has at least four signals, and if there are multiple slave devices, the signal needs more. Some SPI variants use only three lines--SCLK, SS and bidirectional Miso/mosi, but the SS line is still to be and from the device to a pair. In addition, if the SPI is to implement a multi-master device structure, the bus system requires additional logic and circuitry. Building system bus with IIC the only problem is a limited 7-bit address space, but the new standard for this problem has been resolved-using 10-bit addresses. From the 1th, theIIc is the obvious big winner .

second, data throughput/transmission speed

If high-speed data transmission must be used in the application, then the SPI is an inevitable choice . Because the SPI is full duplex, the IIC is not. The SPI does not define speed limits, and generally implementations can reach even more than ten Mbps. IIC has the highest speed of fast + mode (1 Mbps) and high-speed mode (3.4 Mbps), the latter mode also requires additional I/O buffers, is not always easy to implement.

Thirdly, the elegance of

IIC is often said to be more elegant than SPI. To be fair, we are more inclined to think that both are equally graceful and robust. The elegance of IIC lies in its uniqueness-the use of a lightweight architecture for multi-master quorum and device routing. But for the engineers in use, understanding the bus structure is more laborious, and the bus performance is not high.

The advantage of SPI is that its structure is fairly straightforward, easy to implement, and has good extensibility. The simplicity of the SPI is not as elegant as it is due to the need to build a useful communication platform with SPI and to construct specific communication protocol software on top of the SPI. In other words, to obtain the characteristics of the SPI-specific and IIC--high-speed performance, engineers need to pay more labor. In addition, this self-defined work is completely free, which also explains why there is no official standard for SPI. Both IIC and SPI provide good support for low-speed device communication, but theSPI is suitable for data flow applications, while IIC is better suited for multi-master device applications of "byte devices" .

Summary

In the Digital communication protocol cluster,IIC and SPI are often referred to as "small" protocols , compared to Ethernet, USB, SATA, pci-express and other transmission speeds up to hundreds of megabytes per second of the bus. However, what we can't forget is what the various bus uses are. The "Big" protocol is used for communication between the entire system outside the system, "small" protocol is used for communication between the chips in the system, there is no indication that the "big" protocol is necessary to replace the "small" protocol . The existence and prevalence of IIC and SPI embody the philosophy of "good enough". Responding to the text, IIC and SPI are so popular that it is an essential tool for any embedded engineer.

[SPI&I2C] Introduction to I²C and SPI protocols