Xilinx-based Synthesize

Xilinx-based Synthesize

The so-called synthesis means to translate design inputs such as the HDL language and schematic diagram into logical connections (I .e., network tables) between logical units registered with, or, non-users and RAM and triggers ). Optimize the logical connection generated based on the target and requirement (constraints.

ISE-XST

XST is a comprehensive tool developed by Xilinx. We can integrate and implement the input, simulation, and pin allocation.

Double-click Synthesize-XST to complete the synthesis. Generally, there are three results:

Simulation completed

Warn warning

ERROR

Warn generates a yellow alert on Synthesize-XST, and Error is marked in red.

After integration, you can use the XSTView RTLSchematicsTool to view the RTL-level structure.

Synthesize Proprtties

[Optimization Goal]: Optimization Goal. This parameter determines whether the overall tool gives priority to the design based on the area or speed. The area priority principle can save the logical resources inside the device, that is, to use the serial logical structure as much as possible, but this is at the cost of speed. The speed-first principle ensures the overall working speed of the device, that is, the parallel logical structure is adopted as much as possible, but this will waste a large amount of internal logical resources of the device. Therefore, it sacrifices logical resources.

[Optimization Effort]: how hard the optimizer works. There are two options: [normal] and [high. For [normal], the optimizer only performs general optimization on the logical design. The result may not be the best, but the overall and optimization process is executed quickly. If [high] is selected, the optimizer repeatedly optimizes and analyzes the logical design and generates the most ideal synthesis and optimization results, this mode is usually used for high performance and final design; of course, it takes a long time to integrate and optimize it.

[Use Synthesis Constraints File]: Use a comprehensive constraint File. If this option is selected, the constraints file XCF is valid.

[Synthesis Constraints File]: A Comprehensive constraint File. This option is used to specify the XCF path of the XST integrated constraint file.

[Global Optimization Goal]: Global Optimization Goal. Optional attributes include [AllClockNets], [Inpad To Outpad], [Offest In Before], [Offest Out After], and [Maximm Delay]. This parameter is only valid for FPGA Devices. It can be used to select between set registers, between input pins and registers, and between registers and output pins, or the logic optimization policy between the input pin and the output pin.

[Generate RTL Schematic]: Generate a register transfer-level view file. This parameter is used to generate the RTL view of the comprehensive results.

[Write Timing Constraints]: Write time series Constraints. This parameter is only valid for FPGA and is used to set whether to pass the time series constraints used to control the synthesis in the source code of HDL to the NGC network Table file. This file is used for layout and wiring.

HDL language options

[FSM Encoding Algorithm]: Finite State Machine coding Algorithm. This parameter is used to specify the encoding method of the finite state machine. Options include [Auto], [One-Hot], [Compact], [Sequential], [Gray], [Johnson], [User], [Speed1], and [None] encoding. method, the default encoding method is [Auto.

[Safe Implementation]: adds security mode constraints to implement finite state machines, and adds additional logic to change state machines from invalid to valid. Otherwise, they can only be reset, there are two options: [Yes] and [No]. The default value is [No].

[Case Implementation Sytle]: Condition Statement Implementation type. This parameter is used to control the XST integrated tool to interpret and deduce the conditional statements of the Tilde. The options include [None], [Full], [Parallel], and [Full-Parallel]. The default value is [None]. The differences between the four options are as follows: (1) [None], XST retains the prototype of the Condition Statement in the program without any processing; (2) [Full], XST considers the Condition Statement to be complete to avoid the occurrence of latches. (3) [Parallel], XST considers that the branch cannot be generated in the condition statement and does not use the priority encoder. (4) [Full-Parallel], XST considers the Condition Statement to be complete and has no branches inside, and does not use latches and priority encoders.

[RAM Extraction]: memory extension. This parameter is only valid for FPGA and is used to enable and disable RAM macro interfaces. The RAM macro interface is allowed by default.

[RAM Style]: RAM Implementation type. This parameter is only valid for FPGA and is used to select whether block RAM or distributed RAM is used as the implementation type of RAM. The default value is [Auto].

[ROM Extraction]: read-only memory extension. This parameter is only valid for FPGA and is used to enable and disable the ROM macro interface of read-only memory. The ROM macro interface is allowed by default.

[ROM Style]: ROM Implementation type. This parameter is only valid for FPGA and is used to select whether block RAM or distributed RAM is used as the ROM implementation and inference type. The default value is [Auto].

[Mux Extraction]: multiplexing extension. This parameter is used to enable and disable the macro interface of the multiplexing. Based on some preset algorithms, XST can create a macro for each recognized multiplexing/selector and optimize the logic. You can select either of [Yes], [No], or [Force]. The default value is [Yes].

[Mux Style]: multiplexing Implementation type. This parameter is used to select the macro type for implementation and inference multiplexing/selector. You can select either of [Auto], [MUXF], or [MUXCY]. The default value is [Auto].

[Decoder Extraction]: Decoder extension. This parameter is used to enable and disable the decoder macro interface. This interface is allowed by default.

[Priority Encoder Extraction]: Priority decoder extension. This parameter is used to specify whether an encoder macro unit with a priority is used.

[Shift Register Extraction]: Shift Register extension. This parameter is only valid for FPGA and is used to specify whether to use the macro unit of the shift register. The default value is enable.

[Logical Shifter Extraction]: Logical shift register extension. This parameter is only valid for FPGA and is used to specify whether to use the macro unit of the logical shift register. The default value is enable.

[XOR Collapsing]: an exclusive or logical merge method. This parameter is only valid for FPGA and is used to specify whether to combine cascading or logical units into a large logic structure. The default value is enable.

[Resource Sharing]: Resource Sharing. This parameter is used to specify whether to allow reuse of some operation processing modules, such as the adder, subtraction, addition/subtraction, and multiplier when XST is integrated. The default value is enable. If the overall tool selection is speed-first, resource sharing is not considered.

[Multiplier Style]: Multiplier Implementation type. This parameter is only valid for FPGA. It is used when the macro generator uses a multiplier macro unit. Options include [Auto], Block], [LUT], and [Pipe_LUT]. The default value is [Auto]. The selected multiplier Implementation type depends on the selected device.

Special options

Xilinx special options are used to adapt user logic to the special structure of Xilinx chip, which not only saves resources, but also increases the frequency of design operation.

[Add I/O Buffers]: inserts an I/O buffer. This parameter is used to control whether an I/O buffer is automatically inserted to the integrated module. The default value is automatic insert.

[Max Fanout]: the maximum number of fanouts. This parameter is used to specify the maximum fan-out number of signals and network cables. Here, the selection of fan-out numbers is directly related to the design performance and needs to be selected properly.

[Register Duplication]: Register replication. This parameter is used to control whether to allow register replication. Copying registers with high fan-out and time series that do not meet the requirements can reduce the number of buffer outputs and logical series, change some characteristics of the time series, and increase the design frequency. By default, register replication is allowed.

[Equivalent Register Removal]: Delete the Equivalent Register. This parameter is used to specify whether to delete registers with equivalent transfer-level functions, which can reduce the use of register resources. If a register is specified using Xilinx hardware primitives, it will not be deleted. The default value is enable.

[Register Balancing]: Register allocation. This parameter is only valid for FPGA and is used to specify whether to allow the balanced register. Options include [No], [Yes], [Forward], and [Backward]. The register flattening technology can improve the timing conditions of some designs. [Forward] is the Forward register flattening, and [Backward] is the Backward register flattening. After the register is flattened, the number of registers used increases or decreases accordingly. Registers are not flat by default.

[Move First Flip-Flop Stage]: Move the front register. This parameter is only valid for FPGA and is used to control whether to allow the previous register to be moved during register configuration. If [Register Balancing] is set to [No], the setting of this parameter is invalid.

[Move Last Flip-Flop Stage]: Move the back-level register. This parameter is only valid for FPGA and is used to control whether to allow the next-level register to be moved during register configuration. If [Register Balancing] is set to [No], the setting of this parameter is invalid.

[Pack I/O Registers into IOBs]: the I/O register is placed in the input/output block. This parameter is only valid for FPGA and is used to control whether to implement the registers in the logic design using the internal registers of IOB. Input and Output registers are distinguished in IOB of Xilinx FPGA Series. If the first or last level register in the design is implemented using the IOB internal register, the path from the IO pin to the register can be shortened by about 1 ~ 2ns transmission latency. The default value is [Auto].

[Slice Packing]: optimizes the Slice structure. This parameter is only valid for FPGA and is used to control whether to configure the Key Path search table logic in the same Slice or CLB module as much as possible, thus reducing the wiring between LUT. This feature is very useful for improving the design frequency and timing characteristics. By default, the Slice structure can be optimized.

[Optimize Instantiated Primitives]: optimizes the Instantiated Primitives. This parameter controls whether to optimize the instantiated primitives In the HDL code. It is not optimized by default.

The preceding three parts are used to set comprehensive global targets and overall policies, HDL hardware syntax rules, and Xilinx-specific structural attributes.