Go Introduction to FPGA--basys2 generation of pseudo-random gold codes for development boards

This article original, reproduced please indicate the source: http://www.cnblogs.com/risten/p/4166169.html

1. System principle

The frequency control word selects phase stepping to generate the address of the access ROM, thus controlling the output waveform and frequency of the DAC. The entire system consists of clock generation, phase accumulation, ROM, and DAC. Limited to the BASYS2 Development Board, this time replace the output DAC with 8 LED lights display.

2. System Design

2.1 Clock Generation

1 library IEEE; 2 Use IEEE. Std_logic_1164.all; 3 Use IEEE. Std_logic_arith. All; 4 Use IEEE. std_logic_unsigned. All; 5  6 Entity Clock_gen is 7 port (8         CLK        :    in        std_logic; 9         rst        :    in        std_logic;10         Clka        :    out    std_logic11         ); End clock_gen;13 architecture behavioral of Clock_gen IS15 Signal    CNT        :    integer;16 signal    clk_reg    :    std_logic;17 begin19 clka<=clk_reg;20 Process (Clk,rst) begin22 if    (rst= ' 0 ')    then23     cnt<=0;24     clk_reg<= ' 0 '; elsif    ( CLK ' event and clk= ' 1 ') then26     if (cnt=250000) then    --Generate clock for 0.01s27         cnt<=0;28         clk_reg<=not clk_reg;29     else30         cnt<=cnt+1;31     end If;32 End If;33 end Process;34 end behavioral;

2.2 Phase accumulation (address generation)

1 library IEEE; 2 Use IEEE. Std_logic_1164.all; 3 Use IEEE. Std_logic_arith. All; 4 Use IEEE. std_logic_unsigned. All; 5  6 Entity Phase_adder is 7 ports (8         Clka        :    in        std_logic; 9         rst        :    in        std_logic;10         f_level    :    in        std_logic_vector (6 Downto 0), one         addr        :    out    Std_logic_vector (9 Downto 0)         ; end phase_adder;14 architecture behavioral of Phase_adder IS16 signal    cnt        :    ST D_logic_vector (9 Downto 0); begin19 addr<=cnt;20 process (clka,rst,f_level) begin22 if    (rst= ' 0 ')    Then23     cnt<= (others=> ' 0 '); elsif    (Clka ' event and clka= ' 1 ') Then25     cnt<=cnt+f_level;26 End If;27 end Process;28 End behavioral;

2.3 ROM

New source file Select IP Core

Storage type

Storage size

Data initialization

Sine cosine initialization of the Coe file generation (using MATLAB)

1 CLC  2 Clear All  3 Close all    4 x = linspace (0, 2*pi, 1024x768);     % in the interval [0,2*pi] between intervals to take 1024 points   5 y_cos = cos (x);   6 y_sin = sin (x);      7 Y_cos = Y_cos * 2^15;      8 Y_sin = Y_sin * 2^15;      9 FID = fopen (' D:/cos.coe ', ' wt ');   Ten fprintf (FID, '%5.0f,\n ', y_cos);  Fclose (FID);     FID = fopen (' D:/sin.coe ', ' wt ');  fprintf (FID, '%5.0f,\n ', y_sin);       Fclose (FID);

Use Notepad to add at the beginning of the build file

and change the final end to; No.

Once the memory options are set, click Generate.

2.4 LED Display (DAC)

 1 library IEEE; 2 use IEEE. Std_logic_1164.all; 3 Use IEEE. Std_logic_arith. All; 4 Use IEEE. std_logic_unsigned. All; 5 Use IEEE. std_logic_signed. All;    6 7 Entity LED is 8 port (9 data:in Std_logic_vector (downto 0); Led_seg: Out Std_logic_vector (7 Downto 0); End led;13 architecture behavioral of LED IS15 Begin16 process (data) Begin18 if (Signed (data) <-24576) then19 led_seg<= "10000000"; elsif (Signed (data) <-16348) Then21 Led_      Seg<= "01000000", Elsif (Signed (data) <-8192) then23 led_seg<= "00100000", Elsif (Signed (data) <0) Then25 Led_seg<= "00010000", Elsif (Signed (data) <8192) then27 led_seg<= "00001000"; elsif (Signed (data) <16 348) then29 led_seg<= "00000100"; elsif (Signed (data) <24576) then31 led_seg<= "00000010"; else33 le D_seg<= "00000001"; end If;35 end process;36 PNs end behavioral; 

2.5 Top Level Design

 1 library IEEE; 2 Use IEEE. Std_logic_1164.all; 3 4 Entity Top is 5 port (6 clk:in std_logic; 7 rst:in std_logic; 8 F_level:in std_logic_vector (6 downto 0); 9 Led_seg:out std_logic_vector (7 Downto 0); End top;12 architecture behavioral of top Is14 COMPONENT clock_gen15 PORT (clk:in std_logic;17 rst:in std_l         ogic;18 clka:out std_logic19); END component;21 COMPONENT phase_adder22 PORT (23 Clka:in std_logic;24 rst:in std_logic;25 f_level:in ST D_logic_vector (6 Downto 0); Addr:out std_logic_vector (9 Downto 0); END component;29 COMPONENT rom30 PORT (clka:in std_logic;32 addra:in std_logic_vector (9 Downto 0); Douta:out std_log        Ic_vector (Downto 0) 34 ); 0 END component;36 COMPONENT led37 PORT (data:in std_logic_vector (Downto); 39 Led_seg:out Std_logic_vector (7 Downto 0); END component;42 Signal Clka:std_log IC;44 Signal Addr:std_logic_vector (9 Downto 0); signal Data:std_logic_vector (Downto 0); BEGIN48 U1:clock_gen Port Map (Clk,rst,clka), U2:phase_adder port map (clka,rst,f_ LEVEL,ADDR), U3:rom port map (clka,addr,data), u4:led port map (data, LED_SEG); behavioral end;

3. Pin definition

1 net    "CLK"                loc= "B8"; 2 net    "rst"                loc= "P11"; 3  4 net    "f_level<0>"    loc= "L3"; 5 net    "F_level<1>"    Loc= "K3"; 6 net    "f_level<2>"    loc= "B4"; 7 net    "f_level<3>"    loc= "G3"; 8 net    "F_level<4 > "    loc=" F3 ", 9 net"    f_level<5> "    loc=" E2 "; NET" f_level<6> "loc=" N3 "    ; 11 NET "    led_seg<0>"    loc= "M5"; NET "    led_seg<1>" loc= "M11"    ; NET    "led_seg <2> "    P7", "loc=", "    led_seg<3>"    loc= "P6",    "led_seg<4>", "loc=" N5 "    led_seg<5>"    loc= "N4"; Net    "led_seg<6>"    loc= "P4"; Net    "Led_ Seg<7> "    loc=" G1 ";

Go Introduction to FPGA--basys2 generation of pseudo-random gold codes for development boards