In-depth understanding of computer operating systems (notes)

1. Real-time system concepts
2. Compiling the connection
3.at&t Assembly Instruction Learning (GCC)
4. Memory Alignment
5.big-endian Big-endian mode and Little-endian small-end mode
6. Procedure Call

1. Real-time system conceptsFront and rear system

Backstage is a variety of hardware-oriented programs, such as interrupts, timers, Gpio and so on.
The front desk is:

main(){    while(1)    {        ;    }}

Various function implementations are constantly called in the loop.

Code critical section

Refers to the process of an inseparable code, once this part of the code to run can not be interrupted,
In order to ensure that the code can run properly, enter the critical section of the code money needs to shut down, after execution and then open the interrupt.

Task

A task, which is a thread, is a simple program.
The simplest way to communicate between tasks is to use a data-sharing structure.
Inter-Mission Communication pathways: 1) global variables; 2) send a message to another task.
Task switching (context switch)

Priority-based kernels

An inalienable kernel that allows the use of non-reentrant functions.
A stripped-down kernel, where the highest priority task is ready and always gets the right to use the CPU. , you cannot use non-reentrant functions directly.

Mutex conditions

The simplest way to ensure mutual exclusion when working with shared data is to turn off interrupts and interrupts.

Signal Volume

A contractual mechanism.
It's like a key. The task needs to get a semaphore when it runs, and the semaphore is not occupied.

Dead lock

Two tasks wait for each other to release resources.

Synchronous

An interrupt or task triggers another task.

Mailbox

A way to share memory.

Clock beats

Specific periodic interrupts, like the heart of the system.

2. Compiling the connectionFormat of the destination file

To relocate a file:

包含代码和数据  可被用来链接成执行文件或者共享目标文件  linux（.o） windows（.obj）  

Executable file:

包含可以执行的程序系统可以直接执行的文件linux (ELF文件,无后缀) windows (.exe)  

To share a destination file:

包含代码和数据跟可重定位文件和共享目标文件链接，产生新的目标文件动态连接器将共享目标文件与可执行文件结合，作为进程映像的一部分来运行linux（.so） windows (.DLL)

Core dump File

Linux（core dump）

Specific content of the target file
File header

目标文件头

Code section

程序指令(.code /.text)存放程序代码程序

Data section

程序数据(.data /.bss).data段 初始化的全局和局部静态变量.bss段  未初始化的全局和局部静态变量.bss（block started by symbol）符号预留块,没有内容不占据空间

Othe section

还有可能包含的其他段，例 bank data .ect

What are the advantages of separating program instructions and data? 3 points.

3.at&t Assembly Instruction Learning (GCC)

2. Register naming principle:
   Compared to the inter syntax, the/T syntax requires that all registers must be prefixed with the value "%".

4. Operation Code Command format:

   1. Order of Source/destination operands:
      The command representation format in the Intel syntax format is: "OpCode dest, src"; "OpCode target, source"
      AT/t syntax format is expressed as: "opcode src, dest"; "OpCode source, target"

   2. The operand length identifies:
      In the/t syntax, the size of the instruction operand is indicated by adding a suffix after the instruction.
      The suffix ' B ' indicates that the operand is a byte (byte)
      The suffix ' w ' indicates that the operand is a word (word)
      The suffix ' l ' indicates that the operand is a double word (long)
      The Intel syntax for the instruction ' mov ' at at/t syntax must be written according to the actual operation of the object: ' Movb ', ' movw ' or ' movl '.
      Note: If you omit these suffixes at/t, Gas will use the register size to guess the length of the instruction's operand.

   3. Other than that
      ' Far ' is not a gas keyword, so the call or JMP command for far must be prefixed with ' l ', ' far call ' to be written ' lcall ', ' far jmp ' to be written ' ljmp ', ' ret far ' written ' Lret '.
6. Format for constant/immediate number:
   In the/T syntax, the immediate number must be preceded by a prefix of $ to indicate, while the inter syntax is not required.
   In addition, a prefix character * must be added before the constant, and the inter rule is not required.
8. Memory addressing mode:
   In Intel syntax, the following format is used to represent the memory addressing method:
   SECTION:[BASE + INDEX*SCALE + DISP];segment: [Base address + variable address * scale factor + offset]
   Base is the site index register (which can be any universal register),
   Index is the variable address register (any general register except ESP),
   Scale is the proportional constant of the variable-address register,
   The disp is the displacement amount of the base/variable address register.
   The/t syntax uses a different format to represent the addressing method:
   SECTION:DISP(BASE, INDEX, SCALE);segment: offset (base address, change address, scale factor)
10. Labels & identifiers:
    All labels must begin with a letter, Dot, or underscore, and a colon indicates the end of the label.
    The local label uses the number 0-9 followed by a colon, using the local label to follow a character ' B ' (backward reference) or the character ' F ' (forward reference) after the number. Because you can only use the number 0-9 as the local label name, you can define up to 10 local labels. An identifier can assign it to a value. (e.g. ' true=1 ', or using a. Set or. equ directive).
12. Basic Inline assembly format:
    asm("statements");
    For example: ASM ("NOP"); ASM ("Movl%eax,%ebx");
    ASM and _asm_ are exactly the same.
    If there are multiple lines of compilation, each line is added "\n\t"
14. Extended Inline assembly format:
    asm ( "statements" : output_regs : input_regs : clobbered_regs);
    The statement after the colon indicates the input, output, and changed registers.
16. IA32 Integer Register:
    
18. Common directives:
    
    1. Data transfer instruction: Move,push,pop;
    2. Load valid address directive: Leal;
    3. Unary Operation Instruction: Inc (plus 1), Dec (minus 1), neg (minus), not (fetch);
    4. Binary Operation instruction: ADD,SUB,IMUL,IDIVL (signed division), Xor,or,and;
    5. Shift instruction: Sal (left Shift), Shl,sar (arithmetic right shift), SHR (logical right SHIFT);
    6. Jump command: Jmp,je,jne,js,jns,jg,jl,ja,jb,jbe ...

20. Condition code register (single bit):
    CF (carry sign), ZF (0 sign), SF (sign sign), of (overflow flag) ...
    Access condition code directive: Cmp,test,set ...

    t = a + b;cf: (unsigned) t < (unsigned) a;//无符号溢出  zf: t == 0;//零  sf: t < 0;//负数  of: (a < 0 == b < 0) && (t < 0 != a < 0)//有符号溢出  

4. Memory Alignment

2. Why Memory Alignment
   
   1. platform Reason (porting reason): Not all hardware platforms can access arbitrary data at any address, some hardware platforms can only fetch certain types of data at certain addresses, or throw hardware exceptions.
   2. Performance Reason : Memory-aligned, CPU memory access speed greatly increased.

3. Rules for memory alignment

   Many real computer systems limit the location of basic types of data in memory, and they require that the value of the first address of the data be a multiple of a number k (usually 4 or 8), which is called memory alignment, and this k is called the Zimo number of the data type (alignment modulus). When the ratio of one type S pair of Zimo number to the Zimo number of another type T is an integer greater than 1, we call the alignment requirement of type S stronger (strict) than T, while the T is weaker than s (loose). This mandatory requirement simplifies the design of the transfer system between the processor and the memory and improves the speed of reading the data.

   For example, such a processor, every time read and write memory from a certain 8 times times the address of the beginning, read out or write 8 bytes of data, if the software can guarantee that the double type of data from 8 times times the address of the beginning, then read or write a double type of data only need a memory operation. Otherwise, we might need two memory operations to complete this action, because the data might just be across two 8-byte blocks of memory that meet the alignment requirements. Some processors may get an error if the data does not meet the alignment requirements.

   But Intel's IA32 architecture's processors work correctly regardless of whether the data is aligned. But Intel advises that if you want to improve performance, all the program data should be aligned as much as possible.

   1. The Microsoft C compiler (Cl.exe for 80x86) under the Win32 platform uses the following alignment rules by default:
      The Zimo number of any basic data type T is the size of T, which is sizeof (t). For example, for a double type of 8 bytes, the address of the type data is required to always be a multiple of 8, and the Char type data (1 bytes) can start at any address.
   2. GCC alignment rules under Linux:
      The char type data (1 bytes) starts at any point, and any 2-byte data type (such as short) has a Zimo number of 2, while all other data types that are more than 2 bytes (such as long,double) have 4 for the Zimo number. That is, the address of a 2-byte data type (such as short) must be a multiple of 2, while the address of a larger data type (such as int,double, etc.) must be a multiple of 4, which means that the minimum address of the short-type formation must be equal to 0 The minimum two bits of any object or pointer of type int must be 0.

5.big-endian Big-endian mode and Little-endian small-end mode

Defined

1. Little-endian is the low-bit bytes emitted at the lower address of the memory, high-bit bytes emitted in the memory of the higher address.
2. Big-endian is the high-bit byte emitted at the low address of the memory, the low byte is discharged in the memory of the higher address.
3. Network byte order: The TCP/IP layer protocol defines the byte order as Big-endian, so the byte order used in the TCP/IP protocol is often referred to as the network byte order.
4. High/Low byte definition: In decimal we say that the left side is high, the right side is low, and so is the other binary. Take 0x12345678, the bytes from high to low are 0x12, 0x34, 0x56, and 0x78 in turn.

Example Analysis:

unsigned int value = 0x12345678

1.big-endian: Low Address storage high

Bottom of stack (high address)
BUF[3]	(0x78)	Low
BUF[2]	(0x56)
BUF[1]	(0x34)
BUF[0]	(0x12)	High
Top of stack (low address)

2.little-endian: Low-address storage lows

Bottom of stack (high address)
BUF[3]	(0x12)	High
BUF[2]	(0x34)
BUF[1]	(0x56)
BUF[0]	(0x78)	Low
Top of stack (low address)

How to store the CPU memory in Little-endian mode (assuming that the storage starts from address 0x4000)

memory Address	0x4000	0x4001	0x4002	0x4003
Store content	0x78	0x56	0x34	0x12

In Big-endian mode, the CPU memory is stored in the form of

memory Address	0x4000	0x4001	0x4002	0x4003
Store content	0x12	0x34	0x56	0x78

Note: The host order, which we usually call, is followed by the Little-endian rule. Therefore, when the two hosts to communicate through the TCP/IP protocol, it is necessary to call the corresponding function for host order (Little-endian) and network Order (Big-endian) conversion.
Check if the CPU is a big or small end:

int checkCPU(void)  {      union      {          int a;          char b;      }c;      c.a = 1;      return (c.b == 1);  }

6. Procedure Call1. Stack frame structure

Description
The return value is in a position where the relative%ebp offset is 4;
The first parameter is placed at a position relative to the%EBP offset of 8;

Support for procedure calls and returned directives:

The entire assembly process for a procedure call is indicated:

In-depth understanding of computer operating systems (notes)