"In-depth understanding of computer systems" Sixth Week study notes

Fourth Chapter processor Architecture

(i) Summary of knowledge points

I. Y86 instruction set architecture

　　1.The Y86 processor status is similar to IA32and has 8 Program registers:

%eax %ecx , %edx , %EBX %esi Span style= "font-family: the song Body;" >, %edi , %esp %ebp Span style= "font-family: the song Body;" > Each program register of the processor stores one word. %esp be in the stack, out of the stack, Call and return instructions as a stack pointer.

　　2.3 One-digit conditions:ZF,SF, of, They hold information about the effects of the most recent arithmetic or logic directives. The program counter PC holds the address of the currently executing instruction.

　　3. the last part of the state of the program is the status Code stat, which indicates the overall state of the program's execution

　　4.the Y86 instruction set is as follows (all values are indicated in hexadecimal)

　　 5.IA32of theMOVLdirective:IRMOVL,RRMOVL,MRMOVL,RMMOVL. The first letter of the instruction name represents the type of the source. The source can be an immediate number(i), Registers(R), Memory(m), the purpose can be register(R), Memory(m)

　　6. memory references in two memory transfer instructions are base and offset forms

①4 integer operation instructions:addl,subl,andl,xorl

② jump instruction: jmp jle , jl , je jne , jge , JG

③6 Conditional delivery Instructions:cmovle,cmovl,cmove, Cmovne,cmovge,cmovg

④Halt instruction Stop Command execution

　　7. Instruction encoding

① each instruction requires a range of 1-6 bytes. The first byte of each instruction indicates the type of instruction, this byte is divided into two parts, 4 bits per part: High 4 bits is the code part, low 4 bits is the function part

②RRMOVL and conditional delivery have the same instruction code, can be regarded as "unconditional transfer",jmp is "unconditional jump", their function code is 0.

③8 registers corresponding to the 0-7 Register identifier

④ may have an additional register designator byte, specifying one or two registers, these register fields are RA,rB.

⑤ Some instructions want an additional 4 -byte constant number, which can be used as the irmovl of the immediate number data,rmmovl and the offset of the MRMOVL's address designator, as well as the destination address of the branch instruction and the calling instruction (the absolute address). All integers are encoded by a small-end method, which appears in reverse order when the instruction is written in disassembly format.

　　8.y86 Exception

With ". "The first word is the assembler command, which tells the assembler to adjust the address so that it can generate code or insert some data there

　　9. information = bit + context. The 4th chapter, the bit (string) is the Y86 machine code, the context is figure 4-2, the information is the Y86 instruction set.

Second, logical design and hardware control language HCL

　　1. logic gate :&&,| | ,!

　　2. combinational circuits : Many logic gates are combined into a net to construct a computational block. There are two restrictions on building these nets

① the outputs of two or more logic gates cannot be connected together, otherwise the signal on the line may be contradictory, resulting in an illegal voltage or circuit failure

② network must have no ring

　　3. Word-level combination circuit and HCL integer expression

Some bit-level signals represent an integer or some control mode. The combination circuit that performs the word-level computation calculates each bit of the output word with a logic gate based on the individual bits of the input word.

　　4. multiplexer: According to the input control signal value, from a different set of data signals are selected one. A multiplexed function is described with a condition expression.

　　5. the arithmetic / logic Unit is a very important combination circuit, with three inputs, labeled a,B Two data input and a control input. Depending on the settings of the control input, the circuit performs different arithmetic or logical operations on the data input.

　　6. Common format for judging set relationships

Iexpr in {iexpr1,iexpr2,... , IEXPRK}

　　7. Two types of memory devices

① Clock Register (register) store single bit or word, clock signal control register load input value

② Random Access Memory (abbreviated memory) stores multiple words, using the address to select the read or which word to write

　　8.The Y86 processor will hold the program counter (PC), Condition code (CC), program status (Stat ) using the clock register )

　　9. The register file has two read ports (a,B) and a write port (W), and multi-port random access memory allows multiple read and write operations at the same time.

Third, the order realization of Y86

　　1. Organizing the process into stages

① refers to: Fetch the instruction byte from the memory, address the value of the program counter PC

② decoding: Decoding phase reads up to two operands from a register file

③ execution: In the execution phase, the arithmetic / logic unit either executes the operation specified by the value of the Ifun, the valid address referenced by the computer memory, or increases or decreases the stack pointer

④: Data can be written to memory or read from memory during the visit

⑤ writeback: Write-back Stage can write up to two results to register file

⑥ update pc: set the pc as the address of the next instruction

　　2. executing The RRMOVL instruction is similar to performing an arithmetic operation, but does not require a second register operand. Set the second input of the ALU to 0, first add it to the first operand, get Vale=vala, Then write this value to the register file.

3. to irmovl The treatment is similar to the above, except alu The first input is a constant value valc irmovl The program counter must be added 6 . All of these instructions do not change the condition code

4. pushl The instruction starts very much like the previous instruction, but in the decoding phase, with %esp as the identifier of the second register operand valb alu minus the stack pointer 4 4 %esp

　　5.the execution of the POPL instruction is similar to the execution of PUSHL , except that it reads two stack pointers in the decoding phase. popl should read the memory first and then increase the stack pointer.

　　 6.Pagerdirectives,retdirectives andPUSHL,Popsimilar. InstructionPager: ThePagerThe address of the instruction followed by the instructionValppressed into the stack, in the updatePCphase willPCset to call destinationValc. Instructionret: In the updatePCstage, the value to be fetched from the stackValmassign a value toPC.

　　7. The SEQ implementation includes combination logic and two memory devices: Clock register, random access memory.

　　8. Four hardware units-Program counters, condition code registers, data memory, register files-that require explicit control over the timing.

　　9. Calculation principle : The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction. When the clock rises and the next cycle is started, the processor can perform both register write and memory write.

Some instructions (integer operations) set the condition code, and some instructions (jump instructions) read the condition code, but no instruction must both set and read the condition code. Although the condition code is set when the clock rises to the next cycle, they are updated before any instructions attempt to read.

　　10. Common Constants

　　implementation of the 11.SEQ phase

① taking the finger stage

The reference stage includes the instruction memory hardware unit. As the address of the first byte (byte 0) of the PC ,the unit reads 6 bytes at a time from memory , the first byte is interpreted as the instruction byte, and is divided into two 4 The number of digits. The control logic block labeled "icode" and "ifun" calculates the instruction and function code equal to the readout value from memory, or when the instruction address is not valid (imem_ Error indicated), these values correspond to the nop instruction

② Decoding and writeback phase

To access the register file. The register file has four ports and supports simultaneous two reads (Ports A,B) and two writes (E,M), Each port has an address connection and a data connection. Depending on the instruction code icode and the register indicator rA and RB, it may also be calculated based on the execution phase Cnd condition signals.

③ Execution Phase

The execution phase includes the Alu calculation foreach instruction in the first step of the arithmetic / logic unit (alu), and the execution phase includes the condition code register

④ Visit stage

The task of the visit phase is to read or write the program data, the two control blocks generate the memory address and memory input data value, and the other two blocks generate control signals indicating whether read or write operations should be performed. Data memory generates values when performing read operations Valm

⑤ update PC phase

The last stage in the SEQ generates a new value for the program counter, depending on the type of instruction and whether to select the branch, the new PC may be valc,valm , Valp

(ii) The experimental process

Build Yis Environment:

Yis test:

CD Y86-code into the test code, the textbook p239 page code is Asuml.ys, can be compiled through make asuml.yo, asuml.yo is the result of the Assembly

Make all can assemble and run all the code results:

(iii) References

1. "In-depth understanding of computer systems"

2. "Embedded Linux application Development Standard Tutorial"

3. "Y86 Tools　　"

(iv) Learning impressions and summaries

　　This chapter mainly studies the Y86 instruction set architecture, logical design and hardware control Language HCL, Y86 the order of implementation, according to detailed illustrations in the textbook I understand the Y86 assembler and I32 assembler different, Master Y86 command OP1, RRMOVL, IRMOVL, RMMOVL, MRMOVL, PUSHL, POPL and other directives are calculated in the sequential implementation. In the experiment of building the YIS environment, I also encountered the problem of unable to parse the command address at first. After the teacher changed the address of the network to the intranet address successfully connected to the host, but the experiment finally showed Make:***[all] error, I do not know what the error and the cause of the error, hope the teacher corrected.

"In-depth understanding of computer systems" Sixth Week study notes