Introduction to STM32 clock library function RCC_DeInit, stm32rcc_deinit

Introduction to STM32 clock library function RCC_DeInit, stm32rcc_deinit
Void RCC_DeInit (void)
{
RCC-> CR | = (uint32_t) 0x00000001; // enable the internal 8 MHz clock
# Ifndef STM32F10X_CL // STM32F10X_CL indicates the STM32 interconnected series microprocessor.
RCC-> CFGR & = (uint32_t) 0xF8FF0000; // The 27-31 bits in the CFGR register of Other Processors are reserved bits, and the 24-26 bits are MCO bits.
# Else // In the CFGR register of the interconnected processor, 28-31 bits are reserved bits, and 24-27 BITs are MCO
RCC-> CFGR & = (uint32_t) 0xF0FF0000; // initialize the CFGR register. For details, see note 1st.
# Endif

RCC-> CR & = (uint32_t) 0xFEF6FFFF; // initialize the CR register. For details, see note 2nd.
RCC-> CR & = (uint32_t) 0 xFFFBFFFF; // bit 18 = 0. HSE has no bypass. It can be set only when HSE is disabled.


RCC-> CFGR & = (uint32_t) 0xFF80FFFF; // set the CFGR register. For more information, see note 3rd.


# Ifdef STM32F10X_CL // set the interconnected Microcontroller
RCC-> CR & = (uint32_t) 0 xEBFFFFFF;
RCC-> CIR = 0x00FF0000;
RCC-> CFGR2 = 0x00000000;
# Elif defined (STM32F10X_LD_VL) | defined (STM32F10X_MD_VL) | defined (STM32F10X_HD_VL)
RCC-> CIR = 0x009F0000; // initialize the CIR clock interrupt register. For details, see note 4th.
RCC-> CFGR2 = 0x00000000;
# Else
RCC-> CIR = 0x009F0000;
# Endif
}
Note:
1. Bit 26 (27)-24 = 000: The Microcontroller has no clock output;
15-14 = 00: PCLK2 (APB2 clock) is used as the ADC clock after the second division;
13-11 = 000: The HCLK is not divided into two groups, that is, the APB2 high-speed clock PCLK2 is equal to the AHB clock;
Bits 10-8 = 000: the low-speed APB1 clock (PCLK1) is not divided by frequency;
7-4 = 0000: the AHB clock is not divided into two groups, which is equal to the system clock SYSCLK;
3-2 = 00: HSI (Internal High-Speed clock) as the system clock;
1-0 = 00: HSI (Internal High-Speed clock) as the system clock.
2. Bit 24 = 0: PLL disabled;
19 = 0: The Clock detector is disabled. It is enabled when the external clock is ready;
Bit 16 = 0: the external clock HSE is disabled.
3. Bit 22 = 0: the PLL clock is divided into 1.5 times as a USB clock;
Bits 21-18 = 0000: Second-frequency PLL output, which can be set only when the PLL is disabled;
Bit 17 = 0: HSE is not divided, which can be set only when the PLL is disabled;
Bit 16 = 0: The HSI clock is used as the PLL input clock after the 2nd Division. It can be set only when the PLL is disabled;
4. Bit 23 = 1: Clear the clock security system interrupt flag;
Bit 20 = 1: Clear the PLL ready interrupt flag;
Position 19 = 1: Clear HSE readiness interrupt flag;
Bit 18 = 1: Clear the HSI ready interrupt flag;
Bit 17 = 1: Clear the LSE ready interrupt flag;
Bit 16 = 1: Clear the LSI ready interrupt flag.