linux-Core-Interrupt analysis-Interrupt vector table (3)-arm "Go"

Transferred from: http://blog.csdn.net/haolianglh/article/details/51986987

Arm Break Concept

In the 9th chapter of ARM Architecture and programming, there is a concept called "abnormal interruption" in arm, which is a variety of exceptions including external interrupts. Obviously, the concept of "abnormal interruption" of arm system is closer to the concept of "anomaly" in MIPS system.

Since the MIPS system is more similar, the natural arm system has the concept of "abnormal interrupt Entry" and "Exception interrupt vector table".

Non-vectorization interrupt of ARM's abnormal interrupt vector table

The arm system defines 7 types of abnormal interrupts, which are identified in table 9.1 of the ARM Architecture and programming chapter 9th. In the 6th, the abnormal interruption is the uniform entrance of the external interrupt. Obviously, in arm, it is similar to MIPS to implement the non-vectorization of external interrupts. It should be said that the RISC class architecture almost all uses the non-vectorization interrupt.

To quantify abnormal interrupts

Although the external interrupt is not vectorized, the exception interrupt is vectorized. Therefore, ARM also has a so-called exception interrupt vector table.

From the ARM architecture and programming table 9-1, as shown in table 4 1, ARM's exception interrupt vector table can be a high-end vector table, or a low-end vector table, both of which take one. The difference is that the base site is different. The high-end vector is an ARM architecture-selectable configuration that can be configured as a low-end vector or high-end vector via the hardware external input pin, and cannot be changed by instruction to the position of the vector, but if the arm chip has a standard arm coprocessor inside, Then the coprocessor CP15 register C1 bit13 can be used to switch the low-side and high-end vector address, equal to 0 o'clock is the low-end vector, equal to 1 o'clock high-end vector.

Initialization of an exception interrupt vector table

The ARM system initializes the exception interrupt vector table in function early_trap_init (), and assigns a value to the global variable exception_handlers[] member in comparison to the way x86 sets the gate idt_table,mips. Arm's way of comparing the alternative. The way is to start from __vectors_start, until the __vectors_end between the code to copy to Vectors_base address, this vectors_base is actually 0x0000000 or 0xffff0000.

------------------------------------------------arch/arm/kernel/trap.c< Span class= "Hljs-keyword" >void __init early_trap_init (void *vectors_base) {/* exception vector table exception vectors base address */unsigned long Vectors = (unsigned long) vectors_base; extern char __vectors_start[], __vectors_end[]; vectors_page = Vectors_base; /* * Copy the vectors, stubs and kuser helpers (in ENTRY-ARMV. S) * into the vector page, mapped at 0xffff0000, and ensure these * is visible to the instruction stream. */memcpy ((void *) vectors, __vectors_start, __vectors_end-_ _vectors_start); . . .}

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The exception vector table content is the different processing code to take for ARM's 7 exceptions, but the total size of this exception vector table is very small, with each exception having only 4 bytes of code. Thus, in fact, each table entry in the vector table for each exception is a jump instruction or a new value is written to the PC register using the LDR instruction.

------------------------------------------ARCH/ARM/KERNEL/ENTRY-ARMV.globl __vectors_start __vectors_start:arm (Swi sys_error0) THUMB (Svc 
     
       #0) THUMB (
      nop) W (b) Vector_und + stubs_offs ET /* undefined instruction */W (LDR) PC, /* software interrupt SWI, System call */W (b) Vector_pabt + stubs_offset /* Command prefetch Abort */w (b) vector_dabt + stubs_offset /* data Access aborted */W (b) VECTOR_ADDREXCPTN + Stubs_ Offset /* reserved */w (b) Vector_irq + stubs_offset /* external Interrupt Mode */W (b) VEC Tor_fiq + stubs_offset /* fast Interrupt Mode */.globl __vectors_end __ Vectors_end:          
        

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Initialize Large blueprints

The following is an example of HiSilicon's Hi3535 to demonstrate the main process of interrupt initialization for ARM systems.

linux-Core-Interrupt analysis-Interrupt vector table (3)-arm "Go"