Linux Kernel series-6. Memory paging mechanism for operating system development, linux Paging

Linux Kernel series-6. Memory paging mechanism for operating system development, linux Paging

A. Overview

The page size is 4 kb, and each table item occupies 4 bytes. The Register provides the physical base address of the page Directory. The page Directory provides the physical address of all the page tables, each page table provides the physical address of the page it contains.

The page components of the processor are responsible for converting linear addresses to physical addresses. First, it cut the 32-bit linear address sent by the segment component into three segments, which are the high 10 bits, the middle 10 bits, and the low 12 bits. The top 10 digits are the index of the page directory, the middle 10 digits are the index of the page table, and the low 12 digits are used as the intra-page offset.

After a task is loaded, the operating system creates a segment in its 4 GB virtual address space based on its actual situation. The starting address of the segment is 0x00800000, the segment boundary value is 0x5000 in bytes. When the task is executed, the segment register DS points to the segment. Assume that the following command is executed:

Mov edx, [0x1050]

In this case, the segment component outputs a linear address of 0x00801050. When the paging mechanism is not enabled, this is the address of the physical memory to be accessed, but now the paging mechanism is enabled. This is a virtual address. The physical address can be obtained only after the page part is converted.

The physical address of the current task page Directory is in the processor's Cr 3 register. Assume that its content is 0x00005000. the linear address output by the segment management component is 0x00801050, and its binary format is 0000 0000 1000 0000 0001 0000 0101 0000. the 10-bit height is 0000000010, that is, the hexadecimal 0x002, which is the index in the page Directory table. The processor times it by 4 (because each directory item is 4 bytes ), as the offset to access the page Directory. Finally, the processor obtains the physical address 0x00005008 of the page table from the physical address 08001000.

The table items in the page Directory table are referred to as pdns, and the table items in the page table are referred to as PTE. If the paging mechanism is effective, the switch is at the highest PG bit of cr0. If PG = 1, the paging mechanism takes effect.

B. Source Code

PageDirBaseequ200000h; Page Directory start address: Large; Page table start address: 2 M + large: Descriptor PageDirBase, 4095, DA_DRW; Page layout: Descriptor PageTblBase, 1023, DA_DRW | da_limit_4 K; page TablesSelectorPageDirequLABEL_DESC_PAGE_DIR-LABEL_GDTSelectorPageTblequLABEL_DESC_PAGE_TBL-LABEL_GDT; Enable paging mechanism when SetupPaging :...

PageDirBase and PageTblBase specify the location of the page Directory table and page table in the memory. The page Directory table is located at the address of 2 MB and has 1024 table items, occupying 4 kb of space.

The following table lists the formats of 'left' and 'right:

For example, the structure of a table store (such as a table store or a table store) (PDBR) is similar to that of a table store (such as a table store or a table store, that is to say, the page Directory table will be 4 kb aligned. Similarly, the base address of the page table in the pdpa and the base address of the page in the PTE also use a height of 20 bits to represent the 4 kb aligned page table and page.

The running result is as follows:

 

 

【Source code]