0. PrefaceFrom the beginning of learning C language began to contact Makefile, consulted a lot of makefile information but the total feeling did not really master makefile. Assuming that you write a makefile, you always think it's very exhausting.
So deliberately using the blog to summarize the relevant knowledge of makefile. The detailed use of the makefile is illustrated by the sample example.
Examples say that makefile is divided into the following sections. For a lot of other content please refer to "Makefile Index blog post" 1. Only a single C file 2. Contains multiple C files 3. The header file path 4 is required. Add a macro definition 5. Add a system Shared Library 6. Add your own definition Shared library 7. A real Examples of inter-
The Code warehouse--makefile-example code warehouse is located in BitBucket, where you can clone code with TORTOISEHG (GUI tools) or download a zip package directly from a Web page. "This example explains"
This example explains how to add a macro definition in the makefile file.
1.GCC review The macro definition uses the prefix-D to append the macro definition to Cflag during compilation. Macro definitions have two similar spellings "first"-D defines "another"-D defines=condition
2. source file Use two different ways to define the parcel printing function by macro, using #ifdef and #if
#include <stdio.h> #include <test-add.h> #include <test-sub.h>int main (void) { int a = 3; int b = 2; printf ("a=%d\n", a); printf ("b=%d\n", b), #ifdef test_add printf ("a+b=%d\n", ADD (b)), #endif # if test_sub printf ("a-b=%d\n", SUB ( A, b)); #endif return 0;}
3.makefilePlease replace [tab] in the code repository with the makefile file.
# directive compiler and Options cc=gcccflags=-wall-std=gnu99# macro definition DEFS =-dtest_add-dtest_sub=1cflags + = $ (DEFS) # destination file target=test# source file SRCs = test.c ./test-add/test-add.c ./test-sub/test-sub.c# header File Find path inc =-i./test-add-i./test-sub# Destination file Objs = $ (SRCS:.C=.O) # link to run file $ (target): $ (OBJS) # @echo Target:[email protected]# @echo objects:$^[tab]$ (CC)-O [ Email protected] $^CLEAN:[TAB]RM-RF $ (TARGET) $ (OBJS) # Continuous action, please clear the recompile link. Last Run Exec:clean $ (target) [tab] @echo start running [tab]./$ (target) [tab] @echo run End # compilation rule [email protected] represents the target file $< represents the first dependent file%. o:%.c[tab]$ (CC) $ (CFLAGS) $ (INC)-o [email protected]-C $<
4. Detailed Description
The "1" makefile defines a header file in two ways
"First Type"-D defines
"Another"-D defines=condition
The first of these methods corresponds
#ifdef
Do_something ()
#endif
The other method corresponds
#ifndef defines
Do_something ()
#endif "2" DEFS =-dtest_add-dtest_sub=1 in order to illustrate the problem. Two different ways of writing are used here. Both print functions are now run "3" CFLAGS + = $ (DEFS) appended to CFLAGS. It is necessary to emphasize that cflags is just a variable that can be named no matter what the legal name, just to reference it during compilation.
$ (CC)$ (CFLAGS)$ (INC)-o [email protected]-C $<
5. Operation Process"Compile and link" make clean && make "console output" RM-RF test TEST.O./test-add/test-add.o./test-sub/test-sub.o
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test.o-c test.c
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test-add/test-add.o-c TEST-ADD/TEST-ADD.C
Gcc-wall-std=gnu99-dtest_add-dtest_sub=1-i./test-add-i./test-sub-o test-sub/test-sub.o-c TEST-SUB/TEST-SUB.C
Gcc-o Test TEST.O TEST-ADD/TEST-ADD.O test-sub/test-sub.o The output from the console shows that the-D parameter was added during the compilation process.
"Run" a=3
b=2
A+b=5
A-b=1 Finally the results and expectations are exactly the same, makefile get the validation.
6. Summarize "1" Add macro two methods define-D defines and-D defines=condition "2" after attaching to macro definition Cflag
Linux Learning Notes--for example, makefile add a macro definition