Presumably, anyone who knows makefile knows that makefile can invoke a shell script. But when it's actually used, it's not that simple, and some ambiguous places can make you mad. If you don't believe it, you can take a look at a few examples, imagine what these examples will print, write down what you think, and then run these examples on your computer and check it out.
Example one:
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If ["$ (build)" = "Debug"]; Then echo "Build Debug"; else echo "Build release"; Fi
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echo "Done"
Example two:
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@CC =ARM-LINUX-GCC
@echo $ (CC)
Example three:
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cc=arm-linux-gcc
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@echo $ (CC)
Example four:
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SUBDIR=SRC Example
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@for SubDir in $ (subdir); \
Do\
echo "Building" $ (subdir); \
Done
Description
1. The shell script works in Target and is ignored elsewhere. So in example one, a string like "Build Debug" doesn't print at all. The correct wording for example one is:
Example one:
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If ["$ (build)" = "Debug"]; Then echo "Build Debug"; else echo "Build release"; Fi
echo "Done"
2. Make each line of shell scripts as a separate unit that runs in a separate process. In Example II, two lines of shell script run in two unrelated processes, the first process to set CC to ARM-LINUX-GCC, the second process is not known, so the result of the printing is not ARM-LINUX-GCC. The correct formulation of example two is:
Example two:
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@CC =ARM-LINUX-GCC; echo $ (CC)
Or:
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@CC =ARM-LINUX-GCC; \
echo $ (CC)
3. Make is preprocessed before calling the shell, which expands all makefile variables and functions. These variables and functions begin with $. In example three, the script that the shell takes is actually the echo ARM-LINUX-GCC, so the print results are correct.
4. Make preprocessing, all starting with the $, it will not pass. To refer to the shell's own variables, you should start with $$. Also note that the shell's own variables do not require parentheses. The correct formulation of example four is:
Example four:
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SUBDIR=SRC Example
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@for SubDir in $ (subdir); \
Do\
echo "Building" $ $subdir; \
Done