Linux--makefile Writing

Before the preparation of makefile, limited to the beginning of contact, I have been more limited to some rigid format, sometimes it will seem a bit cumbersome. After further understanding of some of the system compiling and linking knowledge, the makefile writing process has some new understanding, so to comb, convenient and more flexible to write makefile.

Limited to makefile understanding, here is a good reference to a better post:Makefile

about Makefile

　　the direct benefit of makefile is that--"automated compilation". once written, you only need a make command, the entire project is automatically compiled, so it is very convenient. The makefile file, however, tells the make command how to compile and link the program. But if you want to use it more flexibly, you should familiarize yourself with some knowledge about the system's compiling and linking to the program.

In general, C, C + + programs, first compile the source file into an intermediate code file. under Linux, the. o file is the Object file, Under Windows, which is the. obj file, this action is called compiling (compile). And then put a lot of. o File synthesis execution file, this action is called link

　　at compile time , the compiler needs the correct syntax, and the declaration of functions and variables is correct. For the latter, it is usually the case that we tell the compiler where the header file is located (in the header file, and the definition is placed in a C + + file), and as long as all the syntax is correct, the compiler can compile the intermediate target file. In general, each source file should correspond to an intermediate target file (. o file or obj file).

　　links are primarily link functions and global variables, so we can use these intermediate target files (. O file or. obj file) to link to our application. The linker does not matter the source file where the function resides, just the intermediate target file of the function . Most of the time, because there are too many source files, compile the resulting intermediate target file too many, and in the link need to clearly indicate the intermediate target file name, which is very inconvenient for compiling, so we want to give the intermediate target file a package, under Windows This package called "Library file", That is, the. lib file, under Linux , is the archive file, or . A files

　　

In general, the source file, the . O file, and the . o file , the executable file. At compile time, the compiler detects only the program syntax, and whether the function or variable is declared. If the function is not declared, the compiler will give you a warning, but you can generate an Object File. When linking the program, the linker will find the implementation of the function in all the. o files, and if not, then the link error code (Linkererrors) will be reported.

　　It is straightforward to say that the resulting executable file is gradually obtained by this "dependency".

Here's an example of how to feel,

 Hello: hello.o    hello.o: hello.c    -C hello.c-o hello.o

Here make, will automatically compile. The resulting executable in this hello depends on hello.o,hello.o dependent on hello.c; Finally found the hello.c can be GCC generated hello.o such a " band ", the target file of the Hello link. o file to execute. It is important to note that when you write the GCC command, you need to add the- C option to ensure that the resulting. o file can be re-linked, or the basic will make an error (some cases such as direct GCC hello.c-o Hello exception).

also note that the commands in the makefile (such as GCC. ), you must start with the [Tab] key , or you will probably make a mistake.

The above example directly linked to an intermediate target file, it is relatively simple, when the source files need to multiple links to multiple intermediate target files, how to look like?

For example, create an addition ADD.C and add.h, a subtraction SUB.C and Sub.h finally main.c to invoke add and sub implementation add and subtract. Now makefile will be like this.

main:main.o add.o sub.omain.o:main.c       -C main.c-o    main.oadd.o:add.cc add.c-o  add.o#加-c. Specifies that the raw is a re-linked. o File  C14>SUB.O:SUB.C    -C SUB.C-o sub.o. Phony:cleanclean:    -rf *.O

Use to see

   

note Several places from above :

　　① When the final target file relies on more than one. O, it will be written to the front with multiple. O dependencies.   Then turn to target: Dependent file gcc ... format, listing all dependencies

　　② because in the above process has generated multiple intermediate. o Files (the actual project is certainly more than a lot of), so each time the compilation completed, need to do a certain cleanup work, then the use of a "clean" (after a moment to elaborate) to clear.

　　③ . phony means that clean is a "pseudo-target". That is, whether or not clean is up to date, be sure to execute it. a small minus sign in front of the RM command means that some files may be problematic, but not ignored. Of course, clean rules are not placed at the beginning of the file, otherwise this will become the default goal of make, and I believe nobody wants to do that. The unwritten rule is that "clean is always at the end of the file."

about Clean:

It's just an action name, a bit like lable in C, with nothing after the colon, so make doesn't automatically look for its dependencies, and it doesn't automatically execute the commands defined later. To execute subsequent commands (not only for clean, other lable also apply), it is necessary to clearly indicate the name of the lable after the make command. Such a method is very useful, we can in a makefile to define the unused compilation or compiler-independent commands , such as program packaging, program backup, and so on.

Here, we can get a general idea of makefile and how to achieve makefile. Okay, so how does make and how does it work with makefile?

How do I execute

1, make will find a file named "Makefile" or "Makefile" in the current directory.

2, if found, it will find the first target file in the file (target), in the example above, he will find "main" This file and put this file as the final target file.

3 if the main file does not exist, or if main is dependent on the. O File modification time is newer than the main file, then it executes the command defined later to generate the main file.

4, If the. o file that main depends on does not exist, then make will find the dependency of the. o file in the current file, and if found, generates an. o file based on that rule. (This is a bit like a stack of procedures)

5, of course, your C files and h files are there, so make generates the. o file and then uses the. O The ultimate task of file life make is to execute the file main.

This is the dependency of the entire make, which makes a layer-by-layer look at the dependencies of the file until the first target file is finally compiled. In the search process, if there is an error, such as the last dependent file can not be found, then make will directly exit, and error, and for the definition of the command errors , or the compilation is unsuccessful, makedoes not ignore. Make just file dependencies, that is, if after I find a dependency, the file after the colon is still absent, then I'm sorry, I'm not working.

Flexible Writing Makefile

From the previous makefile writing, in which we write a dependency on the need to write a shape such as gcc x.c-o x.o generation command, here is OK, if the larger project, so it is too cumbersome, so it is understood that generally in the company specifically written makefile people will not write like that. And the more concise way to write, is to use these few symbols:

$^ on behalf of all dependent files
[email protected] on behalf of all target files
$< represents the first dependent file

so you can put The makefile above is rewritten as

.  Phony:cleanmain:main.o add.o sub.omain.o:main.c        -C $<-o [email    protected]add.o:add.c-C $^-o [email protected]  SUB.O:SUB.C    -C $ ^-o [email protected]clean:    -rf *.o

Because it relies on intermediate target files. O, if makefile becomes complex, then we may forget a place to join and cause compilation to fail. Therefore, in order to makefile easy maintenance, in Makefile we can use constants (see here a lot of people say it as a variable, the individual think it is not changed in the back, because the second call constant better) then you can also define a constant to represent all of the. o files, so you can also write them like this

. Phony:clean = main.o\   //\ escape character         add.o       sub.omain: $ ( Objs  %.O:%. C    -$^-o [email protected]clean:    -rm-rf $ (objs)

Here's the%.O:%.c Presumably can guess, this means that all the. o files depend on the corresponding. c file, which saves several steps.

To this, believe that the smart you, you can more flexible writing makefile. Finally, add something about makefile.

What else is makefile?

1. An explicit rule. Explicit rules describe how to generate one or more target files. This is clearly indicated by the writer of the makefile, to generate the file, the file's dependent file, the generated command.
2. Obscure rules. Because our make has an automatic derivation function, the obscure rules allow us to write makefile in a relatively brief way, which is supported by made.
3. The definition of the variable. In makefile we want to define a series of variables, which are usually strings, which is a bit like the macro in your C language, and when Makefile is executed, the variables are extended to the corresponding reference positions.
4. File instructions. It consists of three parts, one referencing another makefile in one makefile, just like the include in C, and the other is specifying a valid part of makefile based on certain circumstances, just like the precompiled # if in C language And there is a command that defines a multiline. I'll tell you about this part of the story in the next section.
5. Comments. In makefile, just the line comment, like the Unix shell script, is annotated with the "#" character, which is like the "//" in C/s + +. If you want to use the "#" character in your makefile, you can escape it with a backslash, for example: "\#".

In engineering applications, our rules are generally as follows:

　　① If this project is not compiled, all of our C files are compiled and linked.

② If a few C files of this project are modified, then we only compile the modified C file and link the target program.

③ If the header file for this project is changed, then we need to compile the C file referencing the header files and link the target program .

　　So as long as our makefile is well written, all of this is done with just one make command, and the make command automatically intelligently determines which files need to be recompiled based on the current file modification, compiling the required files and linking the target program yourself.

Linux--makefile Writing