mini2440 Bare-Metal MMU (ii) (MMU.C)

Category: Embedded

http://blog.chinaunix.net/uid-26435987-id-3082166.html (EXT)

/************************************************
Name:mmu. C
DESC:
revision:2002.2.28 ver 0.0
************************************************/#include "def.h"
#include "Option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "2440slib.h"
#include "Mmu.h"
//Segment (section) is a storage block of size 1MB
1) Only the sections table is used. Only segment storage blocks are used
2) The Cachable/non-cachable area can is changed by Mmt_default value.
The section, size is 1MB. Segment size is 1MB
extern Char __entry[]; void Mmu_init (void)
{
int i,j;
//========================== IMPORTANT NOTE =========================
This program does not allow remapping of the current stack and code area, if you want the storage area to be freemapping, you need to write yourself a nuanced MMU initialization code    //===================================================================Mmu_disabledcache ();//Disable data caching
Mmu_disableicache ();//Disable instruction cache//To use write-back, be sure to clear the Dcache---------------------------------------------------------------------------------------
| for (i=0;i<64;i++)!!! I want to explain this paragraph in detail!!!! |
| for (j=0;j<8;j++) |
|Mmu_cleaninvalidatedcacheindex ((i<<26) | ( J&LT;&LT;5));//Make the entire Dcache data invalid |
|Mmu_invalidateicache ();Invalidates the entire instruction cache |
| |---------------------------------------------------------------------------------------
#if 0
//In order to quickly complete mmu_init (), Icache opens in this
Mmu_enableicache ();
#endif

Mmu_disablemmu ();//Prohibit MMU
Mmu_invalidatetlb ();//Make the Quick table invalid//MMU_SETMTT (int vaddrstart,int vaddrend,int paddrstart,int attr)
MMU_SETMTT (0X00000000,0X07F00000,0X00000000,RW_CNB); Bank0
MMU_SETMTT (0x00000000,0x03f00000, (int) __ENTRY,RW_CB);//bank0
MMU_SETMTT (0X04000000,0X07F00000,0,RW_NCNB);//bank0
MMU_SETMTT (0X08000000,0X0FF00000,0X08000000,RW_CNB);//bank1
MMU_SETMTT (0X10000000,0X17F00000,0X10000000,RW_NCNB);//BANK2
MMU_SETMTT (0X18000000,0X1FF00000,0X18000000,RW_NCNB);//bank3
//MMU_SETMTT (0X20000000,0X27F00000,0X20000000,RW_CB); Bank4
MMU_SETMTT (0X20000000,0X27F00000,0X20000000,RW_CNB);//bank4 for STRATA FlashStrata Flash is Intel's nor type Flash
MMU_SETMTT (0X28000000,0X2FF00000,0X28000000,RW_NCNB);//bank5
//30f00000->30100000, 31000000->30200000 //The following 3 code is the operation to map the s3c2440 virtual address to the physical address (memory), and 2440 SDRAM is BANK6
MMU_SETMTT (0X30000000,0X30100000,0X30000000,RW_CB);//bank6-1 1M
MMU_SETMTT (0X30200000,0X33E00000,0X30200000,RW_NCNB);//bank6-2 60M
MMU_SETMTT (0X33F00000,0X33F00000,0X33F00000,RW_CB);Bank6-3
MMU_SETMTT (0X38000000,0X3FF00000,0X38000000,RW_NCNB);//bank7 127M

MMU_SETMTT (0X40000000,0X47F00000,0X40000000,RW_NCNB);//SFR 127M
MMU_SETMTT (0X48000000,0X5AF00000,0X48000000,RW_NCNB);//SFR 303M
MMU_SETMTT (0X5B000000,0X5B000000,0X5B000000,RW_NCNB);//SFR
MMU_SETMTT (0x5b100000,0xfff00000,0x5b100000,rw_fault);//not usedif the application tier accesses the area, the MMU will error .
Mmu_setttbase (_mmutt_startaddress);//Write conversion table base address to C2
Mmu_setdomain (0x55555550| domain1_attr| DOMAIN0_ATTR);//write domain access control bit to C3//Last sentence C3 0101 0101 0101 0101 0101 0101 0101 0001
//domain1:no_access, Domain0,2~15=client (AP is checked)
Mmu_setprocessid (0x0);//Off FCSE (Fast context switch)
Mmu_enablealignfault ();//Turn on alignment detection

Mmu_enablemmu ();//Enable MMU
Mmu_enableicache ();//Enable Icache
Mmu_enabledcache ();//When the MMU opens, the Dcache must be opened}
//Attr=rw_cb,rw_cnb,rw_ncnb,rw_fault
void changeromcachestatus (int attr)
{
int i,j;
Mmu_disabledcache ();//Disable data caching
Mmu_disableicache ();//Disable instruction cache
//To use write-back, be sure to clear the Dcachefor (i=0;i<64;i++)
for (j=0;j<8;j++)
Mmu_cleaninvalidatedcacheindex ((i<<26) | ( J&LT;&LT;5));//Make the entire Dcache data invalid
Mmu_invalidateicache ();//Make the entire instruction cache invalid
Mmu_disablemmu ();//Prohibit MMU
Mmu_invalidatetlb ();//Make the Quick table invalid
MMU_SETMTT (0X00000000,0X07F00000,0X00000000,ATTR);//bank0
MMU_SETMTT (0X08000000,0X0FF00000,0X08000000,ATTR);//bank1
Mmu_enablemmu ();//Enable MMU
Mmu_enableicache ();//Enable Icahe
Mmu_enabledcache ();//When the MMU opens, the Dcache must be opened
}
//Set Page table functions
Vaddrstart: Virtual Start Address
Vaddrend: Virtual End Address
Paddrstart: Physical Start Address
attr: Accessing Properties
The mapping of virtual storage space to physical storage space is in memory block: divided into 1mb/64kb/4kb/1kb
A contiguous amount of storage space in the virtual storage space is mapped to a contiguous piece of the same size in the physical storage space.
Storage space Page table, each address transform entry actually records the base of a storage block for a virtual storage space
Correspondence between address and base site of a storage block corresponding to physical storage space

void Mmu_setmtt (int vaddrstart,int vaddrend,int paddrstart,int attr)
{
Volatile U32 *ptt;//Defines a pointer to a page table
volatile int i,nsec;
ptt= (U32 *) _mmutt_startaddress+ (VADDRSTART&GT;&GT;20);//Because the memory block is 1M (20bit), the base address of the page table
Nsec= (VADDREND&GT;&GT;20)-(VADDRSTART&GT;&GT;20);//NSEC: Segment Size
for (i=0;i<=nsec;i++) *ptt++=attr | (((paddrstart>>20) +i) <<20);
//Page table stores access information and the base address of the storage block
(((paddrstart>>20) +i) <<20): Address of the corresponding physical memory page
attr: Access rights and Buffering properties
}Reference URL:http://bbs.21ic.com/icview-127516-1-1.html          http://blog.csdn.net/woshixingaaa/article/details/6255870          http://blog.sina.com.cn/s/blog_651c92d3010107qr.html          http://6xudonghai.blog.163.com/blog/static/336406292008724103317304/

mini2440 Bare-Metal MMU (ii) (MMU.C) (EXT)