The bus between the registers and the operating parts of the CPU "internal" link is called the "internal bus"
The CPU is the same as other "high-speed" functional parts of the computer system, such as memory. Channels and other interconnected buses are called "system buses"
"Medium/low-speed I/O devices" connected to each other bus called "I/O Bus"
Bus characteristics:
Physical characteristics bus root number, bus plug socket shape, pin arrangement, etc.
function features per line function, address bus, data bus, control bus
Electrical characteristics the transmission direction of each line In/out level range is active at high and low levels
Time-characteristic signal effective timing relation
The important indicator for measuring bus performance is bus bandwidth
Set bus clock frequency F, bus data width D byte (B)
The bus bandwidth dr=d*f
Example: A bus in a bus cycle in parallel transfer 4 bytes of data, assuming that the bus cycle is equal to a bus clock cycle, bus clock frequency is 33MHz, bus bandwidth dr=d*f=4b*33*10^6/s=132mb/s
If the 64-bit (b) =8b data is transmitted in parallel in a bus cycle, the bus clock frequency rises to 66MHz,
Then the bus bandwidth is dr=d*f=8b*66*10^6/s=528mb/s adapter is usually referred to as the interface
The adapter can match and synchronize speed between high-speed CPUs and "low-speed peripherals (I/O devices)" and complete all data transfer and control between the computer and peripherals
First, the basic type of bus structure:
① single bus architecture easily expands into multiple CPU systems
② Multi-bus structure embodies the high-speed. Low-speed devices connected to different buses work simultaneously to improve bus small cage packets and throughput, and the change in processor structure does not affect the high-speed bus
CPU Bus (cpu.cache), System bus (main memory) and high-speed bus (LAN, video interface). Graphic excuse. SCSI interface. FireWire interfaces, large-capacity I/O devices) are connected to each other via Bridges (bridge: with Buffering. Conversion. Controlled logic Circuit)
Through the expansion bus interface high-speed bus and the expansion bus (serial mode of operation of the I/O device. Modem excuse Fax interface) connected
Second, by bus function classification
① Address line one-way transfer main memory and device address
② Data line bidirectional data transfer
③ control line Each one-way (all lines, direction is not unique, such as the CPU to the interface or interface to the CPU) used to indicate the direction of data transmission, interrupt control, timing control, etc.
Contemporary bus interior
Data transfer bus (address Data control line)
Arbitration bus (bus request line, bus authorization line)
Terminal and synchronous bus (interrupt operation with priority) interrupt the request line, interrupt the recognition line
Utility line (clock signal line, power cord, ground, system reset line, timing signal line for power-on or power-down, etc.) Pentium Three-level multi-bus structure
CPU bus 64-bit data cable 32-bit Address line synchronous bus with bus clock frequency of 66.6 MHz
Bei Qiao
PCI bus connection high-speed I/O device Module (monitor adapter, network interface Controller, hard disk controller, etc.) 32/64-bit synchronous bus, total clock frequency is 33.3MHz, bus broadband 132mb/s adopts centralized arbitration method
South Bridge
ISA bus connects low-speed I/O devices (keyboard. ROM, mouse controller 8042MPU, real clock/calendar)
In a computer system
Three ways to transfer information:
Serial transmission with only one transmission line, serially transmitted data
Parallel transmission simultaneously transmits multiple bits data (taking into account speed and efficiency, the transmission of information on the system bus using parallel transmission mode)
The function of the I/O Interface (adapter) for the multiplexing of the time-sharing transfer bus (both transmitting the address information and transmitting the data information)
1 Control action: Start off the device, etc.
2 buffering compensates for differences in speed of various devices
3 Status Status: Ready, Busy, error
4 Convert and-string conversion or string-and convert
5 Finishing Special Features: Modifying the word counter or the current memory address register
6 Program interrupts
I/O interface Module atmosphere Serial data interface parallel data Interface two types
Cases:
Serial transmission of the "character", the number of bits per second transmitted bit bits is often called the baud rate, assuming that the data transfer rate is 120 characters/s, "each" a "character" format contains 10 "bits" bit (starting bit, stop bit, 8 data bits), the Q-transmit bit rate is? Elapsed time per bit
Baud rate: 120 symbol/s*10bit/symbol =1200bit/s
Elapsed time per bit: 1bit/(1200bit/s) =8.33*10^-4s=0.833ms
The function module connected to the bus has two forms of active and passive
CPU Module Master-slave can be
The memory module can only be
I/O modules can also make bus requests
The main party can start a bus cycle, each bus operation can only one main party occupy bus control
The slave responds to the main party request, and each bus operation can be one or more from the same time
Multiple devices make use of bus requests, with priority or fair policy for arbitration
The time that the main party continuously controls the bus is called the bus occupancy period
According to the position of the bus arbitration circuit, the arbitration method is divided
① Centralized arbitration:
1_ Chain Query Method (Daisy-chain query: The closest device to the bus arbiter has the highest priority) Advantages: Several lines can be achieved, easy to expand equipment, disadvantage: The inquiry chain of the circuit fault sensitivity
2_ Counter Timing Query Method (counter identifies the device address, whether the separation address matches the determined request) features: Flexibility to increase the number of lines at the expense of
3_ independent Request mode (each shared bus device has a pair of bus request lines BR Bus authorization line BG) A little response time, to determine the response equipment to spend less time, limited order control flexibility. Modern bus standards generally adopt independent request mode
② distributed quorum (based on priority quorum policy)
abi= non-(CN1+CN2+......+CNI) bus One-time information transfer process five stages
Request bus, bus quorum, addressing (destination address), information transfer, status return (or error reporting)
Synchronous timing: (the bus contains a clock signal line, all events appear at the forefront of the clock signal) each module sends or receives information by the agreed clock, which has a higher transmission efficiency. It is suitable for the case that the bus length is short and the access time of each function module is close, the synchronous bus designs the common clock according to the slowest module. When the access time of each module varies greatly, the loss of bus efficiency
Asynchronous timing: The length of the bus cycle is variable, and the response time is not imposed on the function module, allowing both fast and slow function modules to be connected to the same bus, at the cost of increasing the complexity and cost of the bus
Bus data transfer Mode
1_ Read and write operations
Read the data transfer from the main party.
Write data transfer from master-to-side
2_ Block transfer operation
"Burst transfer" (read/write one after the other) from the block of memory (from the party), CPU (main side)
Block length is generally "fixed" to 4 times times the width of the data line (memory word length)
3_ Write-post-read, read-Modify write operations
Write first and then read (check purpose)
Read-Before-write (protection of shared storage resources in a multi-channel program system)
4_ broadcast, wide-set operation
One main party writes to multiple slave (broadcast)
Multiple interrupt (wide-set) multi-bus structure detected by multi-party on-bus completion and OR OR operator
The host bus has a 32-bit address line and 64 is the synchronization bus for the data line.
The PCI bus is a processor-independent "high-speed" peripheral bus that is also a critical inter-tier bus, using synchronous timing protocols and centralized arbitration strategies. With automatic configuration capability, support unlimited burst transmission, the system allows a number of PCI bus. (PCI has three kinds of bridge host bridge, Pci/pci Bridge, Pci/legacy Bus Bridge)
The InfiniBand standard describes new architectures and specifications for data flows between processors and intelligent "I/O devices". The "Switch-based" architecture can connect up to 64,000 servers, storage systems, and network devices. Data transfer rate 2.5gb/s,10gb/s, "up to 30gb/s" for high-cost large-scale computer systems CPU<->I/O Interfaces <-> Peripherals Controllers <-> Peripherals
Basic parts of peripheral devices: storage media, drives, control circuitry
Disk composition: Magnetic recording cutoff, disk drive, disk controller;
Disk drives: Write circuit and solitude circuit, read-write switch, read-write head and head positioning servo system, etc.
Disk controllers: Control logic and timing, data-to-string transformation circuits and string-and-transform circuits
Platters are divided into: Convertible disc type and fixed disc type
The head is divided into: movable head and fixed head
Disk drive
Movable head fixed disc: A piece/Group of platters fixed in the spindle, the disc is not convertible, a head on each side, the access data head along the disk surface radial movement
Fixed head: The disc is not convertible, one head per track. Advantage: Fast access speed, save time to find. Cons: Complex structure
Movable head exchangeable disc: The disc can be replaced and the head can be moved radially along the disk surface. A bit: one-sided can be saved offline, the same type of disc interchangeability
Wen Pan (movable head fixed disc) Advantages: Good dust resistance, high reliability, low environmental requirements, the most representative hard disk memory
Disk drives: Positioning drive system, spindle system, Data conversion system
Disk controller: interface to the host (System-level interface), interface to the device (device-level interface)
The arrangement of tracks and sectors on a disk becomes a format
The outer concentric circle is called the 0 track.
The innermost concentric circle is called N-track.
How many sectors each sector can hold, which is usually determined by the operating system
Automatic arranging (machine more than one disk), track number (cylinder number), record face number (magnetic number), Sector code
Storage density
Track density: number of tracks per unit length along the disk radius (road/inch)
Bit density: Track unit length can record binary code bits (bits per inch) the bit density of the track is larger than the outer track
Surface density (bit/square inch) = Channel density * bit density
Storage capacity (typically in bytes b)
Unformatted Capacity (general) = maximum (inner ring) bit density * Most inner ring track circumference * Total number of tracks
Formatted capacity = number of sectors per channel * Sector capacity * Total Tracks
Data transfer time: The time the data was read from the sector to the host
Disk rotation rate R (rpm), track bytes n transmits "byte B" x;
Average access time Ta= seek time ts+ wait time 1/(2r) + data transfer time (X/RN)
Data transfer Rate (Bytes/sec) =rn = bit density * Disk rotation line Speed v Example:
The disk group has 6 pieces, each two record surface, the most the bottom two faces do not use. Storage area inner diameter 22cm, outside diameter 33cm, road density 40 channel/cm, inner layer density 400 bit/cm, rotational speed 6000 rpm/min
How many cylinders, the total storage capacity of the disk group, data transfer rate?
Valid storage Area 33/2-22/2=5.5cm
Number of cylinders = number of tracks = path density * Effective radius =40 Road/cm*5.5cm=220 Road
Maximum inner ring track circumference =π*22 (cm)
N per Channel information = inner layer density * Most inner ring track circumference =400*π*22=880π (B)
Amount of information per face = number of information * Tracks =880π*220=759880 (B)
Disk group Total Capacity = amount of information per face * Number of polygons =759880*10=7598800 (B)
R speed = 6000 rpm/min =6000 turn/60s=100 to/s
Disk Data Rate dr=rn= RPM * per channel information =345400b/s
The cache uses the data that is accessed by the following principles:
Spatial locality: When some data is accessed, other data near that data may be accessed quickly
Time locality: But after some data is accessed, the data may be accessed again soon
The cache uses SRAM or DRAM,
CPU cache access time is generally less than 10ns, hit rate of more than 95%, the full use of hardware implementation
Disk cache access to a large number of data set, the speed is called CPU cache low, management is more complex, generally with software and hardware to complete together
RAID (Redundant array of inexpensive disks) constructs the basis of data chunking and parallel processing technology, the data is interleaved on multiple disks,
Achieve data parallel storage, cross-storage, CD-ROM storage capacity of large, non-volatile, low cost, mobility, slow, low data transfer rate
MN, SC sec, fr seconds; the optical disk constant line speed reads 75 sectors per second, so the value of FR is the sector area code (0~74) in seconds.
MD Mode Control
0 data area and check area 2336B are all 0, do not log data
1 Recording Data 2048b;288b Check area is 4B detection code (EDC) 8B retention area, 276B error correcting code (ECC)
2 2048+288=2336b all for data storage
Example: CD-ROM on the outer edge of a 5mm wide range due to difficult to record data, generally not practical, so the standard playback time of 60 minutes, the calculation mode 1 and Mode 2 in the case of CD storage capacity is how much
Number of sectors = 60 *60 sec *75 Sector/sec =270000 Sector
Mode 1:270000*2048B=527MB
Mode 2:270000*2336B=601MB magnetic disc mo using magnetic field technology and laser technology can be random write, erase or rewrite information; the magnetic surface of the magnetic disc needs high temperature to change the magnetic pole, very stable at room temperature, the data will not change
Read-only Cd-rom;dvd-rom
Write Wrom fragment write Cd-r,dvd-r one write at a time
Rewritable type magnetic disc mo display: Soft copy output device
Printer: Hard copy output device
Pixels: The basic unit that makes up an image
Resolution: The number of pixels the display can represent
Number of colors: The type of color the display can display
Grayscale: Light and dark differences between pixels displayed in a black-and-white display, different colors in a color display
Storage capacity m= resolution * color depth;
Color depth (bit) =log2 (X-level)
For example resolution 1024*1024;256 level color depth
Color depth =log2 (=8bit)
M=1024*1024*8=1mb
Cases:
Assuming total bandwidth 50% is used to refresh the screen, retain 50% bandwidth for other non-refresh functions, resolution 1024x768, color depth 3B, frame rate (refresh rates) 72Hz, total bandwidth =1024*768*3b*72/s÷50%=2*16588kb/s=324mb/s
To achieve such a memory bandwidth take: Using a high-speed DRAM chip, using a multi-body crossover structure, the flush port and the update port are separated, the internal bus width is referred to 64 bits by 32 bits
Graphic: Subjective, represented and generated by a computer
Image: Objective, camera peripheral speed grading
Slower or simpler peripherals (direct switching)
Slow or medium-speed peripherals (answer-switched)
High-speed peripherals (synchronous timing mode)
Faster synchronous transfer with direct access to memory DMA mode
Procedure Query method: Simple and efficient operation of the CPU
2--program Interrupt mode: High CPU efficiency, slow mass retransmission speed (single-stage interrupt, multistage interrupt) Response sequence hardware decision
3--direct access to Memory DMA mode: High data transfer speed, the transfer rate only receive memory access time limit, need more hardware for memory and high-speed peripherals between the large number of data exchange occasions (select DMA controller, multi-channel DMA Controller)
4--Channel mode: Execute channel instruction, organize peripheral devices and memory for data transfer (select/high-Speed channel multichannel)
Parallel SCSI small Computer system interface, system-level interface, parallel I/O interface, SCSI-3 standard allows connected devices on the SCSI bus from 8 to 16, supporting 16-bit data transfer
Serial I/O Standard interface IEEE1393, significant features data transmission high-speed, real-time, small and easy to install, easy to connect the original code, anti-code, complement, shift code
Non-normalized, no special instructions for order code, mantissa with complement
The offset of the shift code in normalization 2^k, not special description, the order code with the shift code, the mantissa with the complement normalization 0.1 1.0)
The offset of the IEEE754 in the 2^k-1; no special instructions, the order code with the shift code, the mantissa with the original code to seek the complement
Positive sign bit 0 original code, counter code, complement three yards in one
Negative sign bit 1 original code, anti-code (original code negation),
Complement (the original code negation plus 1, or [sign bit 1 variable change ...) change [to the right number of the first 1 unchanged] unchanged])
Special definition Complement 10000000 = 128 =-2^7,00000000=0
Principles of computer composition
