Shell Programming Considerations in Makefile

Reference: http://blog.csdn.net/wanglang3081/article/details/49423105

(1) Makefile is essentially a shell script, that is, each command is a shell process, and the shell process exits when it finishes running.

(2) Shell code line, if there is =, there is no space on either side

(3) The shell in makefile, each line is a process, the value of the variable cannot be passed between peers. So, the shell in Makefile is written in one line, no matter how long. You can write with \ to the branch, the format is a little clearer.

subdir=src exampleall:    in $ (subdir);///        down here is a line of Shell     do /        echo"" $ $subdir; /     Done

(4) The variable in makefile begins with $, using $ (VAR) or ${var} to refer to the definition of the variable. So, to avoid collisions with shell variables, the shell's variables start with $$.

Note: In the makefile reference to some simple variables, we can also use "()" and "{}" to tag the variable names, directly using the "$x" format, which is limited to the case where the variable name is a single character. In addition, automation variables are used in this format. A reference to a generic multi-character variable must be marked with parentheses, otherwise make will use the first letter of the variable name as a variable instead of the entire string ("$PATH" is actually "$ (P) ATH" in makefile). This is different from the way variables in the shell are referenced. A reference to a variable in the shell can be either "${xx}" or "$XX" format. However, a reference to a multi-character variable name in Makefile can only be in the format "$ (XX)" or "${xx}".

pwd | awk " / " ' {print $ $NF} ' )

(5) The shell script can only be invoked in target in makefile and cannot be exported elsewhere. For example, the following code does not have any output.

var="Hello"echo"$ (VAR)"all:   ... ..

As long as the following output

var="Hello" All:    echo"$ (VAR) "     .....

(6) Execute the shell command in makefile, one line to create a process to execute.  This is also why many makefile have many lines at the end of the "; \ "To ensure that the code is one line instead of multiple lines, so that the makefile can be executed in a process.

 for file inch $ (src_file);          Do          "$ $file";               Done

(7) All words in Makefile are interpreted as variables in the makefile. If you need to invoke a variable in the shell (or an anchor in a regular expression), you need to add two $ sign ($$).

Path="/data/"all:    echo ${path}//* Makefile in variables, i.e. "/ Data "*/echo//    variable in shell  */

The first ${path} in the example refers to a variable in the makefile, not the PATH environment variable in the shell, which refers to the PATH environment variable in the shell.

Shell Programming Considerations in Makefile