Writing shell code in makefile is a bit weird, unlike shell syntax, and if you don't understand it, it can be confusing to see makefile. Here's a summary of some.
1: The code that is the same line after the colon of the target item of the makefile file is the shell code.
eg
xx = xx1//Here when makefile code
YY:XX = XX2//This is the makefile code, makefile allow variables to be assigned, the ' = ' sign on both sides of the empty cell
Yy:
XX=XX3//Only here is the shell code, the shell does not allow the ' = ' number on both sides of the space Oh.
There is one exception:
xx=$ (shell code is also the shell)
The shell in 2:makefile, where each line is a process, the value of the variable cannot be passed between peers. So, the shell in Makefile is written in one line, no matter how long.
eg
SUBDIR=SRC Example
All
@for SubDir in $ (subdir); ///Down here is a line of shells
do/
echo "Building" $ $subdir; /
Done
The variables in 3:makefile begin with $, so in order to avoid conflicts with shell variables, the shell's variables start with $$
EG1: Extracts the previous part of/application or/base_class from the current directory path
Project_root_dir = $ (Shell pwd | awk-f '/application|/base_class ' {print $$1} ')
EG2: The $ $subdir in the example above is a variable in the shell, while $ (subdir) is a variable in makefile
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1, in Makefile can only invoke shell script in target, other places can not be output. For example, the following code does not have any output:
Var= "Hello" echo "$VAR" all: .....
The above code will not output at any time, not within target, if the above code is changed to the following:
Var= "Hello" All: echo "$VAR" .....
The above code will execute the echo command when make all.
2. Execute the shell command in makefile, one line to create a process to execute. This is also why many makefile have many lines at the end of the "; \ "To ensure that the code is one line instead of multiple lines, so that the makefile can be executed in a process, for example:
SUBDIR=SRC exampleall: @for subdir in $ (subdir); Do echo "building"; Done
As you can see, each line in the For loop is "; \ "End of.
3. All words that begin with $ in makefile will be interpreted as variables in the makefile. If you need to invoke a variable in the shell (or an anchor in a regular expression), you need to add two $ sign ($$). Examples are as follows:
Path= "/data/" All: echo ${path} echo $ $PATH
The first ${path} in the example refers to a variable in the makefile, not the PATH environment variable in the shell, which refers to the PATH environment variable in the shell.
DIRS = src bin Lib
All
@for I in $ (DIRS); /
Do/
echo "" $ $i; /
Done
Dirs is the makefile variable, and I is the shell variable
The above three points is makefile call Shell should pay attention to the place, write makefile must pay attention to.
Original:
http://my.unix-center.net/~Simon_fu/?p=648
Shell syntax in makefile