Song Baohua talks about one of arm's embedded Linux porting experiences: Basic Concepts

Song Baohua talks about the basic concepts of arm's embedded Linux porting experience

1. Introduction
Arm is short for Advanced RISC Machines (a processor of advanced and streamlined command systems). It is a microprocessor intellectual property (IP) Core provided by arm.
Arm has been applied in various product markets, including industrial control, consumer electronic products, communication systems, network systems, and wireless systems. ARM-based microprocessor applications occupy a market share of more than 75% of 32-bit Proteus microprocessors. Uncover your cell phone, MP3, PDA, and hey, most of them have an ARM-based microprocessor!
Several ARM Kernel series (such as ARM7, arm9e, arm10e, securcore, XScale, and strongarm) can meet the needs of different application fields and penetrate embedded systems into every corner. This is an era of arm!
The following figure shows arm everywhere:

 

Some people have the rivers and lakes ("Wulin rumor") and some embedded systems have the arm.
To build a complex embedded system, hardware alone is not enough. We also need to port the operating system. We usually Build Windows CE, Linux, and Palm OS on the ARM platform, among which Linux has the advantages of open source code.
Shows the relationship between software and hardware in an ARM-based embedded system:

Recently, as the project owner of an Embedded ARM (hardware)/Linux (software) system, I led the project team to do the following:
(1) circuit board design based on the ARM920T kernel S3C2410A CPU;
(2) Build the underlying software platform for ARM processing:
A. Port bootloader;
B. transplantation of the embedded Linux operating system kernel;
C. Create an embedded linux root file system;
D. Write the peripheral Linux driver on the circuit board.
This article will truly repeat the experiences of the author during the development of this project, so as to share with the readers. The first chapter briefly introduces the hardware design of the arm Development Board, the second chapter analyzes the bootloader porting method, and the third chapter describes the transplantation of embedded mizi Linux and the construction of file systems, chapter 4 describes the peripheral driver design. Chapter 5 provides an example of application development on a constructed software and hardware platform.
If you have an Embedded System Development Foundation, you can easily understand the content described in this article. Even if you have never experienced the development of embedded systems, this article will not be a raw one. You can contact the author via email below: 21cnbao@21cn.com.
2. Arm Architecture
ARM microprocessor is a typical feature of the server architecture. It also has the following enhancements:
(L) In each data processing instruction, the arithmetic logical unit (ALU) and the er are controlled to maximize the utilization of ALU and er;
(2) The addressing mode of auto increment and auto increment to optimize the loop in the program;
(3) load and store multiple commands at the same time to increase data throughput;
(4) All commands are executed in a condition to increase the execution throughput.
The ARM architecture is 32 characters long and supports byte (8 bits), halfword (16 bits), and word (32 bits) data types.
The ARM processor supports seven processor modes, as shown in the following table:

Most applications run in user mode. When the processor is in user mode, the executed program cannot access some protected system resources or change the mode. Otherwise, an exception occurs. The use of system resources is controlled by the operating system.
Other user modes are also called privileged modes. They can fully access system resources and change the mode freely. FIQ, IRQ, supervisor, abort, and undefined modes are also called exception modes. The system enters these modes when handling specific exceptions. These five exception modes have their own additional registers to avoid conflicts with programs in user mode when exceptions occur.
Another mode is the system mode. Any exception will not lead to this mode, and it uses the same registers as the user mode. It is a privileged mode for operating system tasks that have access to system resource requests and need to avoid using additional registers.
There are 37 arm registers visible to programmers: 31 general-purpose registers and 6 dedicated status registers set up for different working modes of arm processors, such:

Uses 5-level pipeline operations: Command prefetch, decoding, execution, data buffering, and write-back. ARM9. it sets 16-character data buffering and 4-word address buffering. These 5 levels of streamline have been used by many of the RISC processors and are seen as the "classic" of the RISC structure ".
3. Hardware Design
3.1 S3C2410A Microcontroller
The ARM microcontroller S3C2410A on the circuit board uses ARM920T core, which consists of arm9tdmi, memory management unit MMU, and high-speed cache. Among them, MMU can manage virtual memory. High-speed cache consists of an independent 16 KB address and 16 KB data high-speed cache. ARM920T has two internal coprocessor: cp14 and CP15. Cp14 is used for debugging control, and CP15 is used for storage system control and test control.
S3C2410A integrates a large number of internal circuits and peripheral interfaces:
· LCD controller (supports DNS and tft LCD screen with touch screen)
· SDRAM Controller
· UART in three channels
· 4-channel DMA
· 4 timers with PWM function and an internal clock
· 8-Channel 10-bit ADC
· Touch Screen Interface
· I2C bus interface
· 12 s bus interface
· Two USB host interfaces
· A usb device interface
· Two SPI Interfaces
· SD Interface
· MMC Card Interface
S3C2410A integrates an RTC with calendar functions and a chip clock generator with PLL (mpll and upll. Mpll generates the master clock, enabling the processor to operate at a maximum frequency of 203 MHz. This operation frequency allows the processor to easily run wince, Linux and other operating systems and perform more complex information processing. Upll generates a clock for implementing the USB Module.
Displays the Integrated Resources and peripheral interfaces of S3C2410A:

We need to explain the concepts of the AHB Bus and the APB bus. The purpose of ARM core development is to use it as a processing unit of a complex on-chip system. Therefore, an interface for arm to communicate with other on-chip macro units must be provided. To reduce unnecessary waste of design resources, arm defines the AMBA (advanced microcontroller bus architecture) bus specification, it is a set of standard and open protocols designed for communication between on-Chip Systems Based on ARM cores.
In AMBA Bus Specifications, three types of buses are defined:
(L) AHB-advanced high-performance Mace bus, used for high-performance system module connection, supporting burst mode data transmission and transaction segmentation;
(2) asb-advanced system bus is also used for high-performance system module connection and supports data transmission in burst mode. This is an old system bus format and was later replaced by AHB Bus;
(3) APB-Advanced Peripheral Bus, used for simple connections with low-performance peripherals, generally the second-level bus connected to the AHB or ASB system bus.
Typical AMBA bus systems include:

S3C2410A divides the system's storage space into eight banks, each of which is 128 MB in size and 1 GB in total. The starting address from bank0 to bank5 is fixed and used for ROM or SRAM. Bank6 and bank7 can be used for Rom, SRAM, or SDRAM. The access cycle of all memory blocks is programmable, and the external wait can also extend the access cycle. The Memory Organization of S3C2410A is given:

The data bus, address bus, and chip selection circuit of S3C2410A are provided:

SDRAM control signal and integrated USB interface circuit:

Kernel and storage unit power supply circuit (S3C2410A uses an independent power supply for each part in the chip, the kernel uses 1.8 V power supply, and the storage unit uses 3.3 V independent power supply ):

The JTAG Standard provides a method to test the functions, interconnectivity, and mutual impact of each component on the circuit board through the boundary scan technology, which greatly facilitates the debugging of the system circuit.
The pins of the Test Access Port tap are defined as follows:
· TCK: a dedicated logic test clock. The clock rising edge is used to shift test commands, data, and control signals in serial mode. The downturns are used to shift output signals;
· TMS: test mode selection, which provides effective logic test control signals on the rising edge of TCK;
· TDI: test data input, used to receive test data and test commands;
· TDO: test data output for test data output.
The JTAG interface circuit for S3C2410A debugging:

3.2 SDRAM memory
SDRAM is used to store the Operating System (decompressed from flash) and various types of dynamic data. It uses Samsung's k4s561632, which is a synchronous DRAM of 4mxl6bitx4bank with a capacity of 32 MB. Two slices of k4s561632 are used to implement bit expansion, so that the data bus width reaches 32 bit, the total capacity reaches 64 MB, and the address space is mapped to the bank6 of S3C2410A.
All input and output of SDRAM are synchronized with the rising edge of the system clock Cl K. The input signal Ra S, ca s, and we are combined to generate the SDRAM control command. The basic control command is as follows:

Prior to the specific operation, SDRAM must first set the mode register through the Mrs command to determine the mode of operation such as column address delay, burst type, burst length, and so on. Then, use the act command to activate the corresponding address group, enter the row address at the same time, and then enter the column address through the RD or WR command to read or write the corresponding data. After the operation is complete, run the PCH command or BT command to stop the read or write operation. When no operation is performed, the data must be refreshed by using the arn command at intervals to prevent data loss.
The connection circuit of SDRAM is provided:

3.3 flash memory
Nor and NAND are two major non-loss flash technologies on the market.
Nor features in-chip execution (xip, execute in place), that is, applications can run directly in flash memory without having to read the code into system Ram. Nor transmission efficiency is very high, in 1 ~ 4 MB of small capacity has a high cost efficiency, but the low write and erase speed greatly affects its performance.
The NAND structure provides a very high unit density, achieves a high storage density, and writes and erases quickly. The difficulty of using NAND lies in Flash management and special system interfaces. The S3C2410A is embedded with the NAND flash controller.
S3C2410A can be started from nor flash on gcs0 (16-bit or 32-bit) or from NAND Flash. It must be set through the up/down when power-on om0 and om1:

A piece of nor flash (28f640) and NAND Flash (k9s1208) are used in the system. The circuit is as follows:

3.4 serial port
The UART Controller is integrated into the S3C2410 system to implement String Conversion. The conversion between the CMOS/TTL level and RS232 is also required for the external:

3.5 Ethernet
The Ethernet control chip uses cs8900a produced by Cirrus logic, which features flexibility. Its physical layer interface, data transmission mode, and working mode can be dynamically adjusted as needed, the internal register settings are used to adapt to different application environments. It complies with the ieee803.3 Ethernet standard and has a 10base-t connection port for transmitting and receiving low-pass filtering. It supports AuI interfaces of 10base2, 10base5, and 10base-f, and can automatically generate headers and perform CRC checks, automatic resend after the conflict.
Cs8900a supports I/O and memory modes. When cs8900a has a hardware reset or software reset, it will become the 8-bit working mode by default. Therefore, to enable cs8900a to work in 16-Bit mode, the system must provide the High-position enable pin (/sbhe) to the bus before access) A level from high to low, and then from low to high.

3.6 USB Interface
The USB system consists of a USB host, a USB hub, and a USB device. USB and host system interfaces are called host controllers. They are implemented by combining hardware and software. The root hub is integrated in the host system to provide USB connection points. USB devices include hubs and function devices ).
S3C2410A integrates USB host and USB device. The external connection circuit is as follows:

3.7 Power Supply
Low dropout is a step-down converter in DC/DC converters. It has the advantages of low cost, low noise and low power consumption. In addition, it requires few peripheral devices, usually only 1 ~ 2 bypass capacitors.
On the circuit board, we use two LVS to convert 5 V to 3.3 V (storage interface level) and 1.8 V (ARM kernel level.

The up monitoring circuit uses a max708 chip to provide power-on, power-down, and Buck reset outputs and low-level valid manual reset outputs:

3.8 others
Sn74lvth62245a provides bus drive and buffer capabilities:

S3C2410A integrated LCD display control circuit, external egress interface:

The Touch Screen has resistance type and Capacitive Type. In essence, it is a sensor that converts the Contact Position of the finger on the screen into an electrical signal. When the finger is on the screen, the electrical resistance or capacitance of the contact position changes. Then, the electrical variation is detected to obtain the Coordinate Position of the finger. Use the integrated AD function of S3C2410A to convert the electrical signal to the screen coordinate. The touch screen interface is as follows:

The keyboard uses the programmable I/O Ports of the CPU directly. If the mxn keyboard is connected, m + n programmable I/O ports are required. The software scans the keyboard and recognizes the buttons:

3.9 overall architecture
Presents the overall design framework of the ARM processor and peripheral circuit:

4. Summary
This chapter describes the basic components of the circuit board hardware design based on the S3C2410A ARM processor, and provides overall preparation for subsequent chapters.
Original article: http://dev.yesky.com/6/2527006.shtml.