The Linux Drive series arm assembly

When learning Linux on the arm platform, you will encounter arm assembly instructions, which are different from the 8086 assembly instructions, which are noted here to avoid forgetting, and to analyze code written by assembly instructions after learning the assembly instructions.

A, relative jump instruction B, bl

B, BL instructions are implemented short jump, BL instruction will be executed in the link register R14 the address of the next instruction.

Second, data transmission instructions MOV

The MOV instruction assigns a number of registers to another register, or passes a constant to another register.

such as: MOV r0,r1//The value in R1 is passed to R0,mov r0, #0xff//The constant 0xFF is passed to the R0 register.

The constants passed by the MOV instruction must be able to be represented by an immediate number, which can be passed with LDR instructions when it is not known whether a number can be passed with an "immediate number".

such as: Ldr R0,=0xff.

Iii. Memory Access Instructions STR, LDR, LDM, STM

The LDR instruction reads the number from memory into the register, and the str instruction passes the number in the register to memory, and the number of LDR and STR instruction operations is 32 bits. LDM, STM is a bulk memory access instruction that can access multiple data with one instruction. Here's the s3c2440 datasheet.

{COND} indicates the execution condition of the instruction

Save the memory address in Rn if there is one behind! The address of the next memory cell is updated after the instruction executes

<Rlist> Register list for LDM directives that are equivalent to fetching the data of memory into a register in the list, the STM directive is equivalent to putting the values in the registers in the list into memory.

{^} has two meanings: if the <Rlist> has a PC register, it means that after the instruction executes, the value of the SPSR register is automatically copied in the CPSR register, which is often used to return from the interrupt handler function. If there is no PC register in <Rlist>, {^} indicates that the operation is in user-mode registers, not in privileged mode.

The register in the instruction list corresponds to memory: The register at the bottom of the number corresponds to the low address memory unit, and the number corresponds to the high address of the deposit element.

Iv. Add and subtract instructions Add, sub

Example: Add R0,r1, #0xff//r0=r1+0xff Sub r0,r1, #0xff//= R0=r1-0xff

V. Program Status register Access instruction MSR, Mrs

ARM has a program status register CPSR, which is used to control the operating mode of the processor and to set the total switching of interrupts.

MSR cpsr,r0//copy R0 to CPSR

Mrs R0,CPSR//copy CPSR to R0

VI. Pseudo-directive

. GLOABL _start

_start:

. text

. extern Main

. GLOABL defines a program in this file as a global

. extern references a variable or function to this file

. text indicates that the following statements are part of a code snippet

Eight, uboot START process analysis

After reading Vedon's book and video, we have a new understanding of the assembly instructions and bootloader workflow, and the bootloader of our contact is the BIOS of the computer. Bootloader is a program that moves the code on our hard drive to a specified location in memory.

When it comes to the concept of hard disk memory, we first have a general understanding of the storage space of s3c24xx or other microprocessors. I do the experiment is mainly used 2440, below also 2440 to explain. In 2440 we generally use three kinds of storage devices: SDRAM, Nandflash, Norflash. These three storage devices compared to our normal PC is:sdram====> memory, (Nandflash, Norflash) ====> hard disk, the difference between Nandflash and Norflash is mainly the former can not directly run the code, The latter code can run directly but not write data, so we often put Nandflash stored program, Norflash storage data.

There is a dedicated storage controller for storage space 2440,

　

Generally we put Norflash, Nandflash are connected with nGCS0, and then choose OM0, OM1 choose which way to start, if you choose Norflash our code will start from the Norflash 0 address to execute, If you choose Nandflash our code will be the processor will nandflash the first 4k copy to the inside of the chip 4k RAM, and then the program in the internal 4k RAM execution, the copy process is a hardware process, the chip internal automatic completion. Because only 4k size if our program is less than 4k, we directly let it in the chip internal RAM execution, if our code is larger than 4k, we usually use 4k size program to Nandflash inside the rest of the program directly copied to SDRAM (0x3000 0000) execution.

Our bootloader must be greater than 4k, saying that if we run in Nandflash we have to copy bootloader to SDRAM in the 4k size code and then Nandflash in SDRAM. The Kernerl copy in the SDRAM to complete the kernel startup, the large process as mentioned above, but specifically in the implementation of the process has a lot of small details.

8.1 bootloader Pre-launch preparation

1. Close the watchdog

2. Set the clock

3. Initializing SDRAM

4. Reposition to copy bootloader code from Nandflash to SDRAM

5. Execute Main

= = = = = The work done in the main function

1, initialize the serial port (because to load the kernel needs to print some information, the kernel does not have serial port initialization code, so need to be initialized before the kernel boot)

2.

　　

The Linux Drive series arm assembly