Zhejiang University of Technology computer college-Digital Logic Circuit Course Design Report

Digital Logic Circuit Course Design Report

 

I. experiment content

 

1. 12-digit counter design.

2. Design of Digital Frequency meters.

Ii. 12-digit Counter Design

1. design requirements

Use 74ls192 to design a 12-in-order addition counter. the counter value ranges from 01 to 01 ~ 12-cycle, with 7-segment LED digital display. Verify with the DeII lab board.

2. Schematic Design

1. Use 74ls192 as the high and low positions of the counter, 74ls192 on the left as the low position, and 74ls192 on the right as the high position. the input values A, B, C, and D of the two parts are set to 0, 0, 0, and the input frequency of 74ls192 on the left is 1 kHz.

2. Use the 74ls47 decoder to directly translate the input decimal signal into seven display codes, and connect the output interface to the seven display tubes.

3. Use a single or non-gate to implement decimal. When 001011 is generated, port resetting is enabled.

Diagram 1 of the 12-in-order addition counter is shown.

Figure 1 schematic diagram of 12-digit addition counter

3. Procedure

1. Open the quartuⅱ software, create a wizard, and select cycloneiiep2c35f672c8 as the device. Create block digoal/schematic file and cnt12.bdf File

2. Import the components 74ls192 and 74ls47 from the library, connect the map, and modify the name of the input and output pins.

3. Compile the entire process and start the "assigment-pin" menu after making no mistakes, and configure the location of the pin.

PIN-V13, PIN-V14, PIN-AE11, PIN-AD11, PIN-AC12, PIN-AB12, PIN-AF12.

4. Select the "programmer" command under the "Tools" menu in the quartusi software. Before downloading the SDK, configure the hardware. In "hardware setting", select "USB-Blaster" and set the programming mode to "JTAG ", in the "Program/configure" check box, you can click the "Start" button to start the download.

5. Check whether the FPGA is in 12 hexadecimal format.

3. four-digit Digital Frequency Meter Design

1. design requirements

Design a four-digit frequency meter with a frequency measurement range of 0000 ~ 9999Hz. Verify with the DeII lab board.

2. Working Principle of Digital Frequency Meter

When the gate signal (Positive pulse with a width of 1 s) arrives, the gate is opened and the tested signal is sent to the counter through the gate. The counter starts counting. When the gate signal ends, the counter stops counting. Because the gate activation time is 1 s, the counter value is the Tested signal frequency. To make the measured frequency value accurate, the counter must be cleared before the gate is opened. In order to display the frequency value of the display circuit stably, a lock is added between the counter and the display circuit. When the counter count ends, the Count value is sent to the lock through the lock signal.

The control circuit generates three signals under the control of the time base circuit: The gate signal, the lock signal and the reset signal.

Figure 2 schematic diagram of a Digital Frequency Meter

Figure 3 digital frequency Diagram

3. Top-level schematic design of digital frequency meters

The figure shows four different functional modules: cnt10, lat44. decoder and control.

1 The four decimal counters cnt10 form a 10000 hexadecimal counter, which is the measurement range of the frequency meter to 0-9999Hz;

The 2latc4module is used to store counter counting results;

The 3decoder module converts the 8421bcd code output by the counter to the 7-segment display code.

The 4control module is a frequency controller that generates control signals that meet the timing requirements.

Figure 4 top-level diagram of a Digital Frequency Meter

4. Simulation of the underlying modules of the Digital Frequency Meter

(1) counter module Simulation

CLK: Time base signal

CLR: zero signal

CS: chip selection signal, which is counted only when cs = 1.

Figure 5 simulation results of the counter module

(2) simulation of the latch Module

When le = 1, the DD signal is locked to QQ.

Figure 6 simulation results of the latch Module

(3) display the simulation results of the decoding module

Convert the 8421bcd Code passed in by din into a 7-segment display code

Figure 7 decoding module simulation result

(4) simulation results of the control module

The control circuit generates three signals under the control of the time base circuit: The gate signal, the lock signal and the reset signal.

Figure 8 simulation results of the control module

5. Digital Frequency Operation Process

1. Open the quartuⅱ software, create a wizard, and select cycloneiiep2c35f672c8 as the device. Create a VHDL File, and create four modules: cnt10, lat4, decoder, and control.

2. Compile VHDLCode.

Cnt10:

Library IEEE; Use IEEE. std_logic_00004.all; Use IEEE. std_logic_unsigned.all; Entity cnt10 is Port (CLK: In std_logic; CLR: In std_logic; CS: In std_logic; QQ: Buffer std_logic_vector (3 downto 0 ); CO: Out std_logic ); End cnt10; Architecture one of cnt10 is Begin Process (CLK, CLR, CS) Begin If (CLR = '1') then Qq <= "0000 "; Elsif (CLK 'event and CLK = '1') then If (cs = '1') then If (qq = 9) then Qq <= "0000 "; Else Qq <= QQ + 1; End if; End if; End if; End Process; Process (qq) Begin If (qq = 9) then Co <= '0 '; Else Co <= '1 '; End if; End Process; End;

Lat44:

Library IEEE; Use IEEE. std_logic_00004.all; Use IEEE. std_logic_unsigned.all; Entity lat4is Port (Le: In std_logic; DD: In std_logic_vector (3 downto 0 ); QQ: Out std_logic_vector (3 downto 0 )); End lat44; Architecture one of lat4is Begin Process (Le, DD) Begin If (Le = '1') then Qq <= dd; End if; End Process; End one;

Decoder:

Library IEEE; Use IEEE. std_logic_00004.all; Entity decoder is Port (DIN: In std_logic_vector (3 downto 0 ); Led7s: Out std_logic_vector (6 downto 0) ); End; Architecture one of decoder is Begin Process (DIN) Begin Case din Is When "0000" => led7s <= "1000000 "; When "0001" => led7s <= "1111001 "; When "0010" => led7s <= "0100100 "; When "0011" => led7s <= "0110000 "; When "0100" => led7s <= "0011001 "; When "0101" => led7s <= "0010010 "; When "0110" => led7s <= "0000010 "; When "0111" => led7s <= "1111000 "; When "1000" => led7s <= "0000000 "; When "1001" => led7s <= "0010000 "; When "1010" => led7s <= "0001000 "; When "1011" => led7s <= "0000011 "; When "1100" => led7s <= "1000110 "; When "1101" => led7s <= "0100001 "; When "1110" => led7s <= "0000110 "; When "1111" => led7s <= "0001110 "; When others => led7s <= NULL; End case; End Process; End;

Control:

Library IEEE; Use IEEE. std_logic_00004.all; Entity control is Port (CLK: In std_logic; CS, CLR, le: Out std_logic ); End Control; Architecture behav of control is Signal current_state, next_state: std_logic_vector (3 downto 0 ); Constant st0. std_logic_vector: = "0011 "; Constant ST1: std_logic_vector := "0010 "; Constant st2: std_logic_vector: = "0110 "; Constant st3: std_logic_vector: = "0111 "; Constant st4: std_logic_vector: = "0101 "; Constant ST5: std_logic_vector: = "0100 "; Constant st6: std_logic_vector: = "1100 "; Constant st7: std_logic_vector: = "1101 "; Constant st8: std_logic_vector: = "1111 "; Constant st9: std_logic_vector: = "1110 "; Begin COM1: Process (current_state) Begin Case current_state is When st0 => next_state <= ST1; CLR <= '1'; CS <= '0'; Le <= '0 '; When ST1 => next_state <= st2; CLR <= '0'; CS <= '1'; Le <= '0 '; When st2 => next_state <= st3; CLR <= '0'; CS <= '1'; Le <= '0 '; When st3 => next_state <= st4; CLR <= '0'; CS <= '1'; Le <= '0 '; When st4 => next_state <= ST5; CLR <= '0'; CS <= '1'; Le <= '0 '; When ST5 => next_state <= st6; CLR <= '0'; CS <= '1'; Le <= '0 '; When st6 => next_state <= st7; CLR <= '0'; CS <= '1'; Le <= '0 '; When st7 => next_state <= st8; CLR <= '0'; CS <= '1'; Le <= '0 '; When st8 => next_state <= st9; CLR <= '0'; CS <= '1'; Le <= '0 '; When st9 => next_state <= st0; CLR <= '0'; CS <= '0'; Le <= '1 '; When others => next_state <= st0; CLR <= '0'; CS <= '0'; Le <= '0 '; End case; End Process COM1; Reg: Process (CLK) Begin If (CLK 'event and CLK = '1') then Current_state <= next_state; End if; End Process reg; End behav;

3. compile each sub-module. If an error occurs, check whether the VHDL is correct.

4. After the previous step is compiled successfully, perform the simulation. Create a vector waveform file, determine the simulation time (End Time) and grid size, add the input and output nodes (insert node or bus) to the List, and configure the Input Waveform, start simulation ).

5. After the simulation results are correct, generate the corresponding module symbol for use in the top-layer graph.

6. After each sub-module is complete, create fmeter. BDF. Import the sub-modules to the file, and correctly deploy and connect the modules according to the top-level principle diagram. Set fmeter. BDF to top-level and compile.

7. After the previous step is correct, start to allocate pins, enable the pin option, set location for each node, and set rule reference books in this appendix.

8. Open programmer, download the fmeter configuration to the cycloneii chip, and run it on the FPGA panel. Check whether an error occurs. If not, the experiment is successfully completed.

Iv. Experiment experience

1. Problems Encountered

1. After compiling the VHDL code, the compilation always displays errors. Check that the code is correct and re-create the wizard.

Solution: create an independent folder and store the files in it. Otherwise, other irrelevant files in the same directory may affect compilation.

2. After the content is downloaded to FPGA, it cannot run properly.

Solution: when checking the configuration, the chip Model configuration is incorrect. It should be cycloneiiep2c35f672c8.

3. Compile fmeter. BDF but fail.

Solution: When checking for errors, we found that there were redundant line headers and some connections were not actually connected.

2. Experiment gains

3. Suggestions