-1__ processor design for semi-compliant arm soft core processor

My God, this article speaks about the instruction format and transmission of the processor:

[63:61] [60] [59:54] [53:48] [47:42] [41:0]

Conditioncode dataswitch OPCode targetreg secondreg Else

Conditioncode is a conditional code, simplified after the remaining 6 (==,!=,>,<,>=,<=), in turn distributed in 1-6-bit, 0-bit for unconditional execution, which six for if in CPSR corresponding bit is 1, then execute (so convenient and compatible arm).

Dataswitch, if you set 1, then the other part represents a 32-digit or 42-bit address, and if 0 it says only [41:36] represents the register.

opcode for opcode, not explained, attached.

Targetreg is the register that will be assigned the value.

Secondreg is the first operand.

else combines dataswitch with the second operand.

The instruction format is O, then the transmission mode:

Oh, my God. I also wanted to download it in a less stupid way, and spent one months trying to include Virtualjtag,softjtag,in-system Sources and probes Editor. My days, I this version of the quartusii have bug,exec QUARTUS_STP error, the online method is not, TCL script will not write. In-system Sources and probes editor can only be downloaded manually (one). No way, had to use UART

This is a question: serial port up to 8 digits at a time, and instructions have 64 bits, the SPI USB module is too hard to find, eventually only 64-bit instructions can be divided into 10 transmission (why not 8 times). You have to add a sign per byte, or the order (not to mention the original order, easy to mess)). I'll empty the first bit of each byte, first position 1, The back of the place 0. Now that it's all split up, I let the address of this instruction pass through (debug to write instructions multiple times, in the FPGA with the counter can not cover the original instructions, but also easy to error) so a command 20 transmission (do not ask why not the last one of the instructions to leave the spare part of the address, write the compiler too tired).

Soeasy, next article.