--fifo Add Ethernet MAC header at the beginning of IP core

To put it bluntly, the IP core is someone else's hardware module, providing a complete user interface and documentation, more complex examples of engineering, as long as you can use this IP core, the design has been completed half. Easy to say, learn from lengthy English-language documents and non-standard tutorials on the web, and use them flexibly or in the next few stages.

I think the most important points are as follows:

1) provide the correct clock and reset conditions to the IP core;

2) Clear each important user interface function;

3) Master the operation sequence of the required instruction;

4) Know the internal register address and function and configuration method, order;

5) will learn the correct use of IP core from the official example project;

Today speaking of one of the most commonly used IP cores, FIFO. It can be said that it is the basis for FPGA to handle data so flexibly, it is often used for asynchronous clock domain processing, bit width conversion, and data caching. First of all, for beginners and people who have just contacted an IP core, do not pay too much attention to the IP core of each parameter and function, but also do not need to know the internal structure and working principle (before forgetting to use the Ila bar, anyway I do not know how specifically designed) only need to master the most common and most important, Use the IP core to get it done. Let's start with generating the IP core:

In the first page of the Configuration Wizard, you select the interface mode and implementation of the FIFO. Here we use the original interface method. The arrows are implemented in a way that requires asynchronous clock domain processing to select read-write independent clock mode.

The second page needs to be deliberately focused on the selection of the read mode. In fact, this is the first Word Fall through corresponds to the Altera FPGA in the FIFO IP core read mode in the show ahead mode, just another name. The feature of this reading mode is that the first data in the FIFO is continuously sent from the read data port before the read enable is valid. In this mode, the read enable signal is inverted as a "read" signal, the last data is cleared off, let FIFO send the next data. This is done in accordance with the dout and DOUT_VLD-matched output signal mode.

The third page is to configure some optional flag bits, which can be flexibly implemented with some flags and handshake characteristics (which I never use).

The fourth page is optional FIFO cache data counter, since I started to select the asynchronous FIFO mode, so there are two counters here with the read side and the write side clock rising edge in sync. Note that both counters represent the amount of FIFO cache data, but there are some deviations on the clock that must not be interpreted as how much data is written or read.

The final summary page, the front of the parameters and configuration summary. No problem can click OK!

The IP core is generated, and the next step is to use it correctly. We take the Ethernet interface data transfer as a case background, which is usually the architecture of the FPGA logic +MAC IP Core + external PHY chip. If you want the Mac IP core to properly receive data to be sent, you need to packet the data and add the MAC header information.

To simplify the design, only consider adding the Mac head to the packet after the data, that is, the data entered at this time is the length of the Ethernet specification, and has packet format data. Because of the additional information before the data part output, the input data must be cached until the MAC header output is complete before the write data is sent out, so you need to cache the data in FIFO. Further analysis, the packet after the data format is as follows:

Which SOP and EOP are Baotou, packet tail indicator signal, DATA_VLD is the data valid indicator signal. Since the data bit width here is 32 bits, and the smallest unit of data is byte, each 32-bit data does not necessarily contain 4 bytes of valid data, using DATA_MOD to indicate the number of invalid bytes. In order for the output of the module to know when to output a packet, the EOP signal and data signal stitching to the FIFO, so that the output end of EOP into a new cycle. If according to write SOP signal to start sending the MAC head and data part of the flag, imagine when a short packet is followed by a long packet written into the FIFO, the output is correct in sending out a long packet of the remaining data, unable to respond to the short package SOP signal indication, then the short packet is "discarded". In order to avoid packet loss, it is necessary to satisfy the "read and write Isolation rules", that is, FIFO read operation and write operation cannot decide the behavior of the other party according to the situation of one party. Further, the "dual FIFO architecture", using data FIFO cache data, and information FIFO retention instructions, so that the writing side of the indicator signal to write the information FIFO, the data FIFO can be based on information FIFO read side information to determine the behavior of reading, also satisfies the read and write isolation rules.

In this module, you can write the SOP signal on the write side of the information FIFO a directive information, so when the information FIFO non-empty means that there is a packet is coming in, at this time to send the MAC header information, and then read the data FIFO cache data, when the read side of the EOP signal read the message FIFO, The work of adding header information is completed in the loop.

The Mac header information is 14 bytes, and the data bit width is 32 bits, that is, send four bytes at a time, so it is equivalent to the head of three half data. Therefore, when sending the third header data, the lower 16 bits are populated with data, and the data behind is shifted. After this shift operation, the data part is late for a beat output last 16 bits. If there are valid bytes in the last 16 bits, then the current beat of the MAC_DATA_VLD is also valid, and the Mac_data_eop and Mac_data_mod follow the output later, and if there is no valid byte, the output is normal. In the code I use the End_normal and End_lag signals to differentiate between the two cases. It is important to note that the number of invalid bytes contained in the packet after the shift operation also changes. To clarify the idea and timing, draw the core signal sequence diagram:

With the project requirements, design ideas after the Clear module interface list:

To start writing the code:

  1 ' Timescale 1ns/1ps 2 3 module Add_mac_head (4 input CLK, 5 input rst_n, 6 input [31:0] App_Data,   7 input APP_DATA_VLD, 8 input app_data_sop, 9 input app_data_eop, input [1:0] app_data_mod,//Invalid number of bytes 11 Input MAC_TX_RDY,//MAC IP send ready signal output reg [31:0] mac_data, output reg MAC_DATA_VLD, OUTPU T reg Mac_data_sop, output reg Mac_data_eop, Output reg [1:0] mac_data_mod 18); reg [34:0] wdata; Reg Wrreq,rdreq; Reg WDATA_XX; WRREQ_XX,RDREQ_XX reg; reg [1:0] head_cnt; Reg HEAD_FLAG,HEAD_TMP,RD_FLAG,RD_FLAG_TMP; -reg [34:0] q_tmp; [31:0] Data_shift; Wire add_head_cnt,end_head_cnt; Wire Head_neg; [34:0] Q; Wire rdempty_xx; Sop_in Wire; [2:0] Head_len; [111:0] Mac_head; [47:0] Des_mac,sour_mac; Panax Notoginseng Wire [15:0] pack_type; Rd_neg Wire;   39 40  Fifo_generator_0 Fifo_data (CLK),//input wire CLK-Din (Wdata),//input wire [34:0] DIN 43 . Wr_en (Wrreq),//Input wire wr_en-rd_en (Rdreq),//Input wire rd_en. Dout (q),//Output wire [34:0] Dout. Full (),//Output wire full, empty ()//Output wire empty 48); Fifo_generator_1 Fifo_message (CLK),//Input wire clk. DIN (WDATA_XX),//input wire [0:0] din wr_en (wrreq_xx),//Input wire wr_en-rd_en (RDREQ_XX),//Input wire rd_en. Dout (),//OU Tput wire [0:0] dout "full" (),//Output wire full, empty (rdempty_xx)//Output wire empty 58);             59 60//Data FIFO write data [email protected] (Posedge CLK or Negedge rst_n) begin if (!rst_n) 63 Wdata <= 0; (APP_DATA_VLD) wdata <= {app_data_eop,app_data_mod,app_data}; [email protected] (Posedge CLK or NEGEDGe rst_n) begin if (!rst_n) wrreq <= 0; (APP_DATA_VLD) Wrreq <= 1; Wrreq <= 0; [email protected] (Posedge CLK or Negedge rst_n) begin if (!rst_n) + W Data_xx <= 0; if (sop_in) Bayi wdata_xx <= 1; Wdata_xx <= 0; Assign sop_in = App_data_vld && app_data_sop; 87 88//When the write side appears SOP indicates that a packet is being written, at which time the write information FIFO arbitrary data tells the reading side to start sending the MAC header information [email protected] (Posedge CLK or Negedge R St_n) begin if (!rst_n) wrreq_xx <= 0; Sop_in else if (a) Wrreq_xx <= 1; 94 else wrreq_xx <= 0;  The 98//mac header has 14 bytes of data bit width is 32 bits, that is, a data 4 bytes, need to send 4 data (the last data only 2 bytes is the head) [email protected] (Posedge CLK or Negedge rst_n) begin100 if (!rst_n) 101 head_cnt <= 0;102 Else if (add_head_cnt) begin103 if (end_head_cnt) 104 head_cnt <= 0;105 Else 106 head_cnt <= head_cnt 1 ' b1;107 end108 end109 assign Add_head_ CNT = Head_flag && mac_tx_rdy;111 Assign end_head_cnt = add_head_cnt && head_cnt = head_len-1-1;1 Assign Head_len = 4;113 114//Send MAC head flag bit [email protected] (Posedge CLK or Negedge rst_n) begin11 6 if (!rst_n) 117 Head_flag <= 0;118 else if (end_head_cnt) 119 Head_flag <= 0;1 else if (!rdempty_xx &&!rd_flag) 121 Head_flag <= 1;122 end123 124//Read data FIFO label Chi-bit [email protected] (Posedge CLK or Negedge rst_n) begin126 if (!rst_n) 127 Rd_flag <= 0;1 -Else if (end_head_cnt) 129 Rd_flag <= 1;130 else if (RD_EOP) 131 Rd_flag <= 0 ; end133 134    Assign Rd_eop = rdreq && q[34];135 136 [email protected] (*) begin137 if (Rd_flag && Mac_tx_rdy) 138 rdreq <= 1;139 else140 rdreq <= 0;141 end142 143//Read side appear E         OP reads the full version of the message, at this time read the information FIFO144 [email protected] (*) begin145 if (rd_eop) 146 rdreq_xx <= 1;147 else148 rdreq_xx <= 0;149 end150 151//Register head flag bit to find falling edge [email protected] (Posedge cl K or Negedge Rst_n) begin153 if (!rst_n) 154 head_tmp <= 0;155 else 156 head_tmp & lt;= head_flag;157 end158 159 Assign Head_neg = Head_flag = 0 && head_tmp = 1;160 161//Storage Q For shift Operation 162 [email protected] (Posedge CLK or Negedge rst_n) begin163 if (!rst_n) 164 q_tmp <= 0;     165 Else 166 q_tmp <= q;167 end168 169 Assign Data_shift = {q_tmp[15:0],q[31:16]};170 171//mac Head 14 bytes 172 Assign Mac_head = {des_mac,sour_mac,pack_type};173 Assign des_mac = "HD0_17_C2_00_E5_40;//Destination Mac PC NIC Physical Address 174 Assign SOUR_MAC = h01_02_03_04_05_06;//source MAC address is 01_02_03_04_05_06175 assign Pack_type = + ' H 0800;//IP Datagram 176 177 [email protected] (Posedge CLK or Negedge rst_n) begin178 if (!rst_n)     179 rd_flag_tmp <= 0;180 Else 181 rd_flag_tmp <= rd_flag;182 end183 184 Assign Rd_neg = Rd_flag = = 0 && rd_flag_tmp = 1;185 186//Data output 187 [email protected] (Posedge CLK or Negedge rst_n) begin188 if (!rst_n) 189 Mac_data_sop <= 0;190 else if (add_head_cnt &&am P     head_cnt = = 0) 191 Mac_data_sop <= 1;192 else 193 mac_data_sop <= 0;194 end195 196 [email protected] (Posedge CLK or Negedge rst_n) begin197 if (!rst_n) 198 Mac_data_eop < = 0;199 Elseif (End_normal | | end_lag) MAC_DATA_EOP <= 1;201 Else 202 mac_data_eop <= 0;203 end204 205 Assign end_normal = Rd_eop && q[33:32] > 2 ' d1;206 assign End_lag = Rd_neg &amp ;& q_tmp[33:32] <= 2 ' d1;207 208 [email protected] (Posedge CLK or Negedge rst_n) begin209 if (!rs  T_n) Mac_data <= 0;211 else if (add_head_cnt)//Because the MAC is not an integer multiple of 32-bit data, the data needs to be shifted 212 Mac_data <= mac_head[111-head_cnt*32-: 32];213 else if (HEAD_NEG) 214 mac_data <= {mac_head[15:0],q[31: 16]};215 Else 216 mac_data <= data_shift;217 end218 219 [email protected] (Posedge CLK or Negedge rst_n) begin220 if (!rst_n) 221 MAC_DATA_VLD <= 0;222 else if (Head_flag | | rd_f Lag | |     End_lag) 223 MAC_DATA_VLD <= 1;224 Else 225 mac_data_vld <= 0;226 end227 228 Invalid number of output bytes due toData shift at the output, resulting in a change in the number of invalid data 229 [email protected] (Posedge CLK or Negedge rst_n) begin230 if (!rst_n) 231 Mac_data_mod <= 0;232 Else if (end_normal) 233 mac_data_mod <= q[33:32]-2;234 Else I F (end_lag && q_tmp[33:32] = = 2 ' D1) 235 Mac_data_mod <= 1;236 else if (End_lag && Q_tm     P[33:32] = = 0) 237 Mac_data_mod <= 2;238 else 239 mac_data_mod <= 0;240 end241 242 Endmodule

Write test incentive verification function:

 1 ' Timescale 1ns/1ps 2 3 module ADD_MAC_HEAD_TB; 4 5 6 Reg Clk,rst_n; 7 reg [31:0] App_Data; 8 Reg APP_DATA_SOP,APP_DATA_EOP,APP_DATA_VLD; 9 reg [1:0] app_data_mod;10 reg mac_tx_rdy;11 [31:0] mac_data;13 wire MAC_DATA_VLD,MAC_DATA_SO      P,MAC_DATA_EOP;14 wire [1:0] mac_data_mod;15 add_mac_head add_mac_head (CLK), Rst_n (rst_n), 19 . App_Data (App_Data), APP_DATA_VLD (APP_DATA_VLD), App_data_sop (App_data_sop), App_data_eop (App_da TA_EOP), App_data_mod (App_data_mod),//Invalid bytes (mac_tx_rdy),//mac IP send ready signal. Mac_data (mac_d ATA), MAC_DATA_VLD (MAC_DATA_VLD), Mac_data_sop (Mac_data_sop), Mac_data_eop (Mac_data_eop), mac_ Data_mod (mac_data_mod) parameter CYC = 5,34 rst_time = 2;35 Integ Er i;37 initial begin39 clk = 1;40 Forever # (cyc/2.0) CLK = ~clk;41    End42 initial Begin44 rst_n = 1;45 #1; rst_n = 0;47 # (cyc*rst_time); 48         Rst_n = 1;49 End50 initial begin52 #1; app_data = 0;54 App_data_sop = 0;55 App_data_eop = 0;56 App_data_mod = 0;57 APP_DATA_VLD = 0;58 Mac_tx_rdy = 1;59 # (CY         C*rst_time); Packet_gen (10,0); Packet_gen (5,0); Packet_gen (15,2); #1000; 64         $stop; end66 packet_gen;68 input [15:0] length;69 input [1:0] invld_num;70             Begin71 APP_DATA_VLD = 1;72 App_data_sop = 1;73 App_Data = "h01020300;74"                 for (i = 0;i < Length;i = i + 1 ' B1) begin75 if (i = = 1) App_data_sop = 0;77 else if (i = = length-1) begin78 app_data_mod = invld_num;79 App_data_eop = 1;80 ENd81 App_Data = App_Data +1 ' b1;82 # (cyc*1); end84 App_data_eop = 0;85 APP_DATA_VLD = 0;86 app_data_mod = 0;87 end88 endtask89-Endmodule

Continuous input of three different lengths of messages, here in order to design reuse, with a parameterized task to encapsulate the excitation message. When you need to enter a message, you can simply call the Packet_gen task to implement a packet with different lengths and different number of invalid bytes. Observe the output waveform:

The Mac side outputs three pack documentation data as follows:

You can see that the Mac side data is sent correctly. This blog post is primarily about FIFO applications, where only behavioral simulations are made, and readers can use them flexibly and add them to their projects.

--fifo Add Ethernet MAC header at the beginning of IP core