--I2C (iv) 7bit slave address of the bus

Clock stretching (stretching)
Clock stretching pauses a transmission by pulling the SCL line down. The transfer continues until the SCL line is released high. Clock stretching is optional, in fact most slave devices do not include the SCL driver, so they cannot stretch the clock.
From a byte-level perspective, a device may accept data in fast mode, But more time is needed to store the bytes received or to prepare another byte to be transferred. The slave can pull the SCL line down after accepting and answering bytes in a handshake to force the host into the wait state to know that the slave is ready for the next byte of transmission.
From a bit-level perspective, the devices on the I²C bus can reduce the bus clock by increasing the low cycle of each clock. So each host can adapt to the internal operating rate of the device.
In HS mode, handshake processing can only be used at the byte level.

Slave address and r/w bit
The following figure is the format of the data transfer:

After the start condition (S), send the slave address. The address is 7bit, and the next 8bit is the read-write bit,0 of the data, and 1 reads. See below for details:

The data transfer is terminated by the host-generated termination condition (P). However, the host can also generate a duplicate start condition (Sr) and address another slave without first terminating the condition,
The possible data transfer formats are as follows:
The master-transmitter is transmitted to the slave-receiver. The transmission direction is constant. From-the receiver answers each byte. as follows:

After the first word, the host reads the data from the slave machine. After the first answer, the primary-transmitter becomes the master-receiver and the slave-receiver becomes the slave-transmitter. The first answer is still generated by the slave. The host generates the rest of the answer. The host sends an NA before the terminating condition is generated.

Composite mode. Change direction during transfer, start condition and slave address are repeated, and read and write bit to reverse. If the primary-receiver sends a duplicate start condition, it sends a NA before this.

Attention:
1. The composite mode can be used for example in the control of the serial memory. Be sure to write the address inside the memory when the first data byte is opened. After the start condition and the duplicate from address, the data begins to transfer.
2. Automatically increasing or decreasing the previously accessed memory location is determined by the device's designer.
3. Each byte is followed by an answer bit, denoted by a or not in the diagram.
4. The I²c-bus-compatible device must restart their bus logic when they receive a start condition or a repeating start condition, and they expect to send the slave address even if the starting conditions are not in the correct format.
5. Immediately following a termination condition after starting the condition is not a valid format. Many devices are designed with this in mind and can be handled.
6. Each device connected to the bus is determined by a unique address. Usually a simple master-slave relationship, but there may be multiple slaves that can receive and respond at the same time, such as multicast. Here is an example of NXP's pca9546a. (PCA9546A is a 4-channel bidirectional multiplexer and switch based on the I²c-bus control produced by NXP Semiconductors.) The pca9546a can be used to extend the SCL/SDA input to 4-way SCL/SDA output, and after the internal control register is configured, the simultaneous selection of the downlink I²c bus and the upstream-i²c bus communication can be made. )