017Makefile Engineering Management

1, why need makefile?

With makefile and make, you can combine many jobs into a very simple command: make;

Make enables the entire program to compile, link only one command (make) to complete;

　　

The work of make is mainly dependent on a file called Makefile. The makefile file describes the rules for compiling, linking, and so on throughout the program. These include which source files in the project need to be compiled and how to compile, and how to eventually produce the executable file we want.

2. Makefile constituent rules

Rules are used to describe how to generate a target file in the following format:

Target:prerequisites

Command

Goal: Reliance

Command

Special Note: The command needs to use the "tab" key space

　　

Example:

led.elf:led.o

Arm-linux-ld-tled.lds-o led.elf LED.O

In makefile, those objects that contain only commands and no dependencies are called pseudo-targets (phony targets)

. Phont:clean

Clean

rm-f Hello main.o func.o

". Phony "clean" target declared as pseudo-target

3. Makefile Composition-ultimate goal

(1) How do I execute a rule individually when there are multiple rules in a makefile?

Make (space) the name of the target

(2) If the user does not specify a rule to execute, make defaults to the first rule in Makefile, and the goal in this rule is called: the final goal;

　　

4. Makefile Rules-variables

Before using variables:

APP1:APP1.O FUNC1.O FUNC2.O

GCC app1.o func1.o func2.o-o App1

APP2:APP2.O FUNC1.O FUNC2.O

GCC app2.o func1.o func2.o-o app2

After using the variable:

OBJ=FUNC1.O FUNC2.O

APP1:APP1.O $ (obj)

GCC app1.o $ (obj)-O App1

APP2:APP2.O $ (obj)

GCC app2.o $ (obj)-O app2

In a makefile, multiple occurrences of the component can be replaced with variables;

Makefile, the variable has no type, does not need to define it, directly assigns the value to be able;

The name of the variable can be arbitrarily taken;

OBJ is the variable name, followed by the assignment number =, the left and right sides do not have a space, in the makefile is not allowed to have such a space;

When assigning a value to a variable, the direct variable name, the value of the assignment can be;

But when we refer to this variable, we use $ (variable name)

In makefile, users can also use default variables that are already defined in the system, in addition to defining their own variables.

$^: On behalf of all dependent files

[email protected]: represents the target

$<: Represents the first dependent file

Before use:

Led.o:led. S

Arm-linux-gcc-g-O led.o-c led. S

After use:

Led.o:led. S

ARM-LINUX-GCC-G-o [email protected]-C $^

5. Makefile composition-General rules

How do you combine these rules into a common rule when there are many similar rules in a makefile?

%.O:%. S

Before use:

Led.o:led. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Main.o:main. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Func.o:func. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Features: The same as the command, the name of the target and the name of the dependency is only the suffix is not the same

Can be written as:

%.O:%. S

ARM-LINUX-GCC-G-o [email protected]-C $^

% represents any two of the same name

6, Makefile use tips-to go back to display

To echo: Save time

Echo: The command is printed when the command is executed

For example, do clean will print out: RM *.o *.bin *.elf

Method: Add the @ symbol before the command!

Func.o:func. S

@arm-linux-gcc-g-o [email protected]-C $^

7, Makefile use tips-file name

The make command looks for a project file named Makefile or makefile by default in the current directory, and when the name is not for either of these, you can use the following method to specify:

Make-f file name

Run command: Make-f file name when running as a whole

When executing an instruction individually: for example, make clean should be written as: Make-f file name Clean

　　

　　

017Makefile Engineering Management