17th Chapter Routing Switch Programming
MTU = 64KB After all, it is ideal, it is difficult to achieve at this stage, involving more problems, synchronization with large networks, flow balance, time slot switching. So, APO still decides MTU = 48E = 1536B, including Head 2E, frame synchronization head 8 B, tail CRC 4B, etc. the valid contents of the packet (without the head) are 45E = 1440B. Head 2E = 64B, where Mac head 14B, IP head 18B, tcp/udp/icmp head 32B.
The second layer switch is mainly designed for storage and forwarding, and the switch over three layer is based on the time slot switching of 256-bit differential bus. We know that the SATA3.0 differential serial bus speed of up to 6GBPS, theoretically 256 bits can be 1.5Tbps; or 6ge/s. Then, the transmission of a maximum of 48E of a packet, the time slot 48e/6ge/s = 8ns, the upper Port 2, the subordinate port 48, we need 50 time slots to do a cent exchange. In the 400ns time of 50 slots, there are 50 packets exchanged (read and write), which can theoretically reach the speed of 125 million packets per second/s. The average port speed is 30Gbps, in the backbone of the use, you can reduce the number of ports to improve speed, such as 15 ports, then the port speed can reach 100Gbps. The use of increasing the number of buses to 512 is difficult, another method is to increase the clock frequency, so that the differential serial bus speed of 12GBPS, so that the speed can be as fast as the back plate speed of 3000Gbps. Well, draw it out, and do it in a different matter! To know the speed of light 1ns walk 0.3 meters, the port, the bus must be integrated into a piece of IC is possible, so that the distance is micron, so that, clock synchronization, string-and conversion problems to solve, but also need to have a light-electricity, electricity-light conversion circuit. The cost of soaring, this is a professional nail house thing, this article is not discussed.
First, the port hardware design
Needless to say, there must be a port receiving circuit: A 256-bit conversion, a minimum of 48E receive buffer, the packet IP header 1E hardware judgment and interrupt circuit, 256-bit differential bus interface, control circuit and so on. There are also port emission circuits: 256-bit conversion to string, minimum 48E transmit buffer, target of packet IP header and source reversal circuit and interrupt circuit, 256-bit differential bus interface, control circuit, etc.
1. Hardware judgment and interrupt circuit
Each port has a flag register flag, the lower 16 bits are the device number and port number, and the high 16 bits are the flags. All the signs are hardware-generated. FLAG.29-24 has a flag 1, the interrupt signal is generated, for the two layer switch, interrupt signal to the CPU (using the storage and forwarding mechanism), for the three-layer switch, interrupt signal to the hardware bus time-division switching controller (for speed, direct hardware processing).
BU32 FLAG; Port Flag Register.
flag.31 TLS, 1, three-layer switch, 0, two-layer switch.
flag.30 FSP, 1, packets from the upper port, 0, packets from the subordinate port.
flag.29 BTD; If the packet header Emac.type low 11-bit length value is greater than 1536B, the package is too large flag
flag.28 Icmpapo; High 5 bits is the protocol identifier, and if it is 0, then the ICMPAPO flag is placed.
flag.27 TTL0, if the TTL-1 is 0,ttl0 1.
flag.26 DTP; discard package flags.
flag.25 TBE; send buffer empty flag.
flag.24 Dphe; the packet has entered the receive buffer and reaches the elevator port (high-speed data bus is readable).
flag.23 dpbe; packet header 2E has entered the receive buffer.
flag.22 MF; segment flag, 0 is the last segment or no segment.
flag.21 TSOP; If the packet emac.dladd!= the link address of the node, and FSP = 0, then the forwarding flag to the upper port is Tosp set, and if Tosp and FSP = 1, then the drop packet flag is set.
flag.20 HTN; if Tsop = 0, is the packet of this network segment and the packet Emac.mda = The MAC address of this node, then, hit this node flag HTN the position. If htn and Icmpapo = 1, then the discard package flag is placed.
flag.19 SDI; sending flag.
flag.18 RVI; receiving flag.
flag.17-16 RATA; receive send rate: 10m/100m/1g/10gbps.
flag.15-6 DEVN; device number.
flag.5-0 Portn; Port number. 0, 1 is the superior port, the other subordinate port.
2. Control circuit and Differential bus interface
For a Layer two switch, it is how the CPU reads and writes the port transceiver buffers. For a three-layer switch, the port transceiver buffer reads and writes the allotted timeslot, as instructed by the hardware bus controller.
Two or two-layer switch programming
Layer three switches are hardware-implemented and are not discussed in this article. The storage and forwarding mechanism requires the CPU to manipulate, in fact, we do not need a complex operating system, just a simple interrupt program implementation. Interrupt Source In addition to 50 ports, there is a rs232/rs485, or Mac, such as control port, and timer interrupt. Here, can not be said too detailed, just by imagination Introduction. Can be used 32-bit CPU, or single-chip microcomputer to achieve specific.
main{//main program, accounting for 2W of memory space.
init ();//user CPU initialization, on-chip RAM initialization, attribute table initialization
L:
JMP L;//Idle Process method, infinite loop.
}
//
There are 50 port flag registers in the CPU core, and a 64-bit port interrupt register. Each MAC Port has a Port MAC address Table Mac_tab:mac address, traffic and activity flag, host name. Each port has a send packet buffer of 756E (approximately 16 packets) in memory.
//
pirq{//Mac Port Interrupt program
}
To be continued .....
17th Chapter Routing Switch programming
