(2) power on sequence & BIOS entry

Here we will use desktop platform to describe (the power-on sequence of notebook platform involves EC. For details, refer to "power on sequence" in the Forum"Article); Also, the rough flow (rough process) is described, and the detailed sequence diagram varies slightly according to the design.

<Power-on Sequence>

-Aux (additional interface ?) Power OK

-Main Power OK

-PCI Reset

-Sb state-machine runs...

-Nb state-machine runs...

-CPU power-Good OK

-CPU Reset

-1st code-read by CPU (<-bios entry point, that is, the CPU will capture the BIOS code at fffff0h for execution)

(* Of course, the BIOS data captured by the CPU at a time is not just a few bytes! Instead, a bunch of data (ex. 64 bytes) will be generated from the extract and the data at fffff0h will be executed .)

From here, the CPU follows the path of CPU-> NB-> Sb-> ROM and captures the code in BIOS Rom sequentially, run fetch-> Decode-> calculate-> store... since then, it is BIOS post stage starts...

<The possible problem is> debug code = "00" or "FF" (that is, the "code" displayed by commonly used BIOS port80 card ")!!!

(In this case, it is strongly recommended that port 80 be dropped at the BIOS entry point (the value can be customized), because even if the BIOS is running, there is still a small segment of code missing port80 from 1st.ProgramCodeIf the system hang is in the meantime, port80 still has no code. Therefore, the first time the BIOS comes in, it will be helpful to determine whether the system hang before BIOS entry point or not !!! )

# Assume system hang 'before' BIOS entry point

Possible causes include:

-Incorrect power sequence: this sequence has spec, which regulates the relative relationship between signals and the time of assert/deassert. Violate spec may cause system hang; h/W or board designer is required for measurement.

-Incorrect power-on frequency

-Incorrect chipset behavior: that is, the State-machine part of Nb/Sb in the above power-on sequence. It is possible that the behavior of this part is not normal. Therefore, H/W designer is required to clarify.

(I have heard that a chipset needs to include several bytes in the BIOS image to config the registers of Nb/SB. These settings will also affect the behavior of the chipset during power-on. Therefore, if these bytes are incorrect, the system hang may also be used)

# Assume system hang 'after' BIOS entry point

=> This is the time for BIOS engineer. debug it... (although some issue is caused by board or H/W ...)

* In this debug mode, if you have a secondary tool (ex. P Debug Card), you can use port80 card if you do not have one!

<Summary>: before entering the BIOS entry point... do not contact me... there is really no way> _ <

* For details about BIOS entry point, refer to the article "tracing BIOS code entry point" in the forum !!!

There are two BIOS entry points for your reference:

1. assume that the BIOS image is 512kbyte. use ultraedit and switch to hex format to open this BIOS image. locate the offset 7fff0 and change the original machine code to the machine code of <mov Al, 66 h; out 80 h, Al>. Save the disk, then burn the image to the original Rom. after the device is started, you can find that port80 is "66 ". (Of course, it cannot be started later... because the BIOS content has been damaged... what you changed is where the 1st CPU captures and executes commands !!!)

2. [Q] is mounted to a kb Rom. If you burn a down-size kb BIOS image to the Rom, and then start the system... what will happen? The reason is... ^_^...

I just want to fill it out. Why isn't the first position of CPU sending only fffff0h? But how many more? In this example, why is it 64 bytes?

The reason is the support of cache. the cache is not subdivided into a single byte, but in block (Bytes bytes. the block size is called cache line size. that is, the number of bytes to be written by the cache. for example, the cache line size is 16 bytes. then we need to read 16 bytes to the cache at a time.

When a cache miss occurs on the CPU (it must be a cache miss on the first boot. the information will be obtained through host bus. at this time, the burst read cycle will be generated to meet the needs of fill cache line. therefore, the cache line size of the CPU shows the number of bytes that the CPU will capture at a time. after P4, the CPU cache line size is 64 bytes, so the CPU will generate a memory read cycle with a burst length of 8. therefore, the CPU output location needs to be reduced. then, the read data can contain data after fffffff0h.

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