(2) I2C bus SDA \ SCL and termination start Conditions

I2C transmits data between devices connected to the bus using only two wires (SDA and SCL. each device is identified by a unique address (whether it is a microprocessor, LCD driver, memory, or keyboard interface) and can be used as a sender or receiver based on the functions of the device. the LCD driver may be a receiver, while the memory can send and receive data. in addition to transmitters and receivers, the device can act as a host or slave when transmitting data. A host is a device that initializes data transmission and generates clock signals. At that time, any device that is addressable is a slave device.

The I2C bus is a multi-host bus. this means that multiple devices that can control the bus can be connected to the bus. the host is usually a microcontroller. We can consider the data transmission between the following two processors connected to the bus.


This example highlights the relationship between the master-slave and receiver-transmitter in the I2C bus. Note that these relationships are not fixed and only dependent on the direction of data transmission at the current time. The data transmission process is as follows:
1. Assume that microcontroller A sends data to microcontroller B.
Microcontroller A (host) Addressing microcontroller B (slave)
Microcontroller A (host-transmitter) sends data to microcontroller B (slave-receiver)
Microcontroller A ends Data Transmission
2. Assume that microcontroller A receives data from microcontroller B.
Microcontroller A (host) Addressing microcontroller B (slave)
Microcontroller A (host-receiver) receives data from microcontroller B (slave-transmitter)
Microcontroller A ends Data Transmission
Even in this case, the host (microcontroller A) generates a sequence and terminates the transmission.
When multiple controllers are connected to the I2C bus, multiple hosts may attempt to initialize data transmission. an arbitration mechanism was designed to avoid confusion. it connects all I2C interface channels to the I2C bus by line and logic.
If multiple hosts attempt to send messages to the bus, when other hosts generate "0", the first host that generates "1" will throw arbitration. the clock signal at the time of arbitration is a synchronous combination of the clock generated by the host connected to the SCL line.
Host devices on the I2C bus are generally responsible for Clock generation. when data is transmitted, each host generates its own clock signal. the bus clock of the host is changed only when the clock line is controlled or arbitrated at low speed from the device.
The following table summarizes some configuration options in the I2C bus:

[1] This also refers to the host used as the slave machine.
[2] clock stretching is a feature of some slaves. If no slaves in the system can stretch the clock (lowering the SCL), the host must design a processing program.
[3] 'bit banging' (software simulation) The start byte should be considered for multiple host systems

SDA and SCL Signals
Both SDA and SCL are two-way lines, which are connected to a forward voltage through a current source or a pull-up resistor. (See) when the bus is idle, both lines are high. the output level of the device connected to the bus must be OD (open drain) or oC (open collector) Door to implement the line and function. in standard mode, I2C bus can transmit data at a speed of kb/s, while in fast mode, it can reach a speed of kb/s. In quick plus mode, the speed is 1 Mb/s, the speed is 3.4 Mb/s in the tell mode. the capacity of the bus limits the number of interfaces connected to the bus.
For a single host application, if no device on the bus can pull down the clock, then the host's SCL output should be a push-pull drive design.


Logic level of SDA and SCL
Because devices with different processes (CMOs NMOS bipolar) can be connected to the I2C bus, low voltage and high level are not fixed but dependent on the corresponding VDD level.

Data Validity
The data on the SDA line must be stable during high clock periods. The data line can change the high and low States only when the clock signal on the line is low. A clock is required for each data bit transmission.


Start and end conditions
All transfers start with a start (s) and end with a stop (P.
The start condition is that SDA ranges from high to low when the SCL is high.
The stop condition is that the SDA is from low to high in the case of high-resolution ratio (SCL ).


The start and end conditions are always generated by the host. the bus is busy after the start condition. after the condition is terminated, the last fixed-time bus is idle. if there is no termination condition, but a repeated start condition (SR), the bus is still busy. in this case, S and Sr are functionally the same.
If the device connected to the bus contains required interface hardware, it is easy to start and terminate the condition detection. however, a microcontroller without such an interface needs to sample the SDA line at least twice in each clock cycle to identify whether there is any level change.