2014 Small-Shuo's application note (via)

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At the end of August to find work in Harbin, Granville Sheng came to be relatively early, it should be the specific date of the September teenager is not very clear, I reported the ASIC logic position in Beijing, the position seems to recruit more people, the propaganda will be more formal, to listen to, there is a man wearing glasses long very Peugeot, I also secretly took a picture--that night on the notice of the second day of the written test, this year's Sheng pen questions and previous years of difficulty, the basic requirements are relatively high, at the same time there will be some more ideas of the topic, the same questions change the question, I generally answer can also, should be 80 points, and finally I will give this year

The second day of the written examination to inform the interview, location in the Zheng Ming Jinjiang Hotel, Harbin has a subway is convenient, from home to take the subway directly can to, an interviewer about more than 40 years old, speak very polite, the question asked is relatively fine, the project asked once again, Let me explain in detail the DDS principle in the waveform generator and the specific modulation mode of analog digital modulation waveform, then asked the asynchronous FIFO, mainly how to judge the empty full, the way of addressing and the use of gray code, and so on, I prepared before the full, basic answer almost, At the end of the interview, the interviewer asked me to go directly to the two side.

Two face interviewer is a small boss in Beijing, he was the first to speak, speak very polite, look at my resume all things basically asked once, including each project content, assume the role and mathematical modeling or esports competition, talk about the comparison speculation, this time I feel hope is very big , really boss directly to the HR call said: I have a young man do not do, I let him go to chat with you, and then introduce me to the HR room.

Three sides of the HR face is basically asked some family situation what, work intentions, salary requirements, I said I did not ask for salary, I feel that the requirements are useless, they will not give you special offer, do not ask and will not be low, I directly say to how much is the line, Granville Sheng this year's master is 1w, hair 15 months or so.  Then she asked some similar to the parents do not agree with you to be Beijing ah what, I basically show the intention is relatively strong, finally HR said we give you an offer, how long do you need to think about it? I said should soon, she said that good, go back to my notice, hope to give you an offer after you can reply as soon as possible, I said no problem.

Well, write here you must think I basically have an offer to hand, in fact, I think so at that time, because together to face ASIC four or five students only I one to 3 face, and other posts have a same situation with me, similar to oral offer, the result? Anxiously waited two days later also did not give an offer, call a people Sheng recruitment team has gone to the next station Changchun, and then asked a classmate only one face firmware brother received offer, then call Wei Sheng HR said we plan to North East District face the unified send an offer, then I was drunk, Without it, say a bunch of things like "you had my word" and then go straight away ....

First of all, I am the impression of the Wei Sheng, because the last had a relationship better than the senior brother to tell me that is also good, the company is doing chips, the CPU official said can be ranked third, after Intel and AMD, but I think it with the gap between the two are still relatively large, but the overall welfare and treatment of the company is OK, I am also one of the main objectives of the job search, in fact, at that time, he gave me an offer I should have signed, helpless people do not give, the last November landlord has signed another, the Sheng hr call me, said if I can consider default on the home, they always welcome me, then want to anyway do not make the unhappy, Just to be polite to him, another case of the same buddies received a call to give them a meal spray: "When want to sign the time why not give an offer?" Does it make any sense to give it to you now? "Haha, I heard a very jiehen, but also for my export gas."

The following gives 2014 years of via-asic logic position of the pen test , no other purpose, is to hope that we can make a reference to work, via is still good.

1. What is the build hold time? What is Recovery,remove?  How are they different? (5 points)

2. What is the competitive risk phenomenon?              How to eliminate? (5 points)

3. What are the similarities and differences between Latch and flip flop? (5 points)

4. How are SETUP and hold violation modified? (5 points)

5. What is the difference between link_library and Target_library in DC? (5 points)

6. How is clock gating implemented (drawing)? If you have multiple representations, you can draw them all. (5 points)

7. Arrange the following 7 operators in order of precedence:! , | , | | , +,^,&,*. (5 points)

8. What is a blocking assignment? What is a non-blocking assignment? (5 points)

9. What are the steps in the IC front-end design process? What software is available at each step? (5 points)

10. A synchronizer is usually used in the design to solve the recovery and removal problems of the asynchronous reset signal, please draw the structure diagram of the Synchronizer. (5 points)

What are the characteristics of the Moore and Mealey state machines respectively? (5 points)

12. How to process the signal cross-clock domain in multi-time domain design? How is a single-bit signal handled? What is the multi-bit-wide data handling? (5 points)

13. What is DFT? Why do we do DFT? (5 points)

14. Please use RTL (Verilog) to achieve the following functions (25 points)

(1) Two clock domain, respectively aclk and BCLK, BCLK frequency is aclk twice times, there is no fixed phase relationship, the corresponding reset signal is: areset_x and breset_x (both are low-effective)

(2) ACLK domain, the single bit input signal data_in do a fixed pattern detection, the fixed pattern is 010100.

(3) BCLK domain, the number of pattern detected count, detected 10 times, hit interrupt, counter clear zero.

15. Refer to the following circuit diagram, assuming that the DFF setup time is 0.3, hold time is 0.2, with the door, or the door, and the non-gate delay=0.2, inverter delay=0.1, please answer the following questions (10 points)

(1) What is the minimum delay in Buffer X? Why?

(2) indicate the critical path.

(3) If the delay of buffer X is taken to the minimum, what is the minimum period of the clock in order to satisfy the timing? Why?

2014 Small-Shuo's application note (via)