20145222 Summary of the sixth week of information security system design (1)

20145222 Summary of the sixth week of information security system design (1) Chapter 4 processor architecture

Command architecture: Byte encoding of commands and commands supported by a processor

4.1y86 instruction set architecture

· Y86: includes defining various state elements, instruction sets and Their encoding, a set of programming specifications, and exception event handling.

· Each instruction in the y86 program reads or modifies certain parts of the processor status.
· Y86 includes eight program registers, three condition codes ZF \ SF \ of, and program counters (PC)
· Y86 uses virtual addresses to reference memory locations. The last part of the program State is the State Code stat, which indicates the overall state of the program execution.

· Note: The condition code is only related to Integer Operation instructions.

· The 4-bit high is the code part, and the 4-bit low is the function part.

'Only the instruction of one register operand is required to set the instruction of the other register to 0xf.

· An important property of the instruction set: the bytecode must have a unique explanation.

· Y86 exception: A. Status Code stat, which describes the overall status of program execution.
B. The code value 1 is named aok, indicating that the program runs normally;
C. Code value 2, named HLT, indicates that an halt command is executed at the processing site;
D. code value 3, named "ADR", indicates that the processor attempts to read from an invalid storage address or write to an invalid storage address. It may be when the command is executed, it may also be when reading or writing data.
E. Exception Handling programs and signal processing programs.

4.2 logical design and hardware control language HCl

· Logical gates are the basic computing elements of digital circuits. Their outputs are a Boolean function that equals their input bits.
· Standard symbols of Boolean functions and, or, and not.

· Integrated circuit: combines many logic gates into a single network to build computing blocks.
· Multiplexing: selects one from a group of different data signals based on the value of the input control signal.

· There are two limitations for building these networks: (1) the outputs of two or more logic gates cannot be connected together (2) the network must be non-circular.

The difference between the HCl expression and the logical expression in C language:

(1) the output of the logic circuit of the combination will continuously respond to input changes. The C expression is evaluated only when the program is executed.
(2) The logical expression of c allows the parameter to be any integer. 0 indicates flase, and any other value indicates true. The logic gate only performs operations on 0 and 1.
(3) The logical expression of C may only be partially evaluated. The logic of combination does not have partial evaluation rules. The logic gate simply responds to input changes.

· The general format for determining the set relationship is: iexpr in {iexpr1, iexpr2 ,......, Iexprk}

· Storage devices are controlled by the same clock. The two types of storage devices include:

Clock register (Register): stores a single bit or word, and the clock signal control register loads the input value
Random Access Memory (memory): stores multiple words and uses addresses to select the words to read or write.

Differences between registers in hardware and machine-level programming:

· In hardware, registers directly connect its input and output lines to other parts of the circuit;
· In machine-level programming, registers represent one of the few addressable words in the CPU. The address here is the register ID. The y86 processor uses the clock register to save the program counter (PC), condition Code (CC), and program status (STAT ).

 

4.3 y86 sequential implementation

· Seq processor: all the steps required for seq execution to process a complete instruction at each clock cycle.

· Organize the processing into stages:

Address: valp: length of the extracted command added to the PC value.
Decoding: Read the registers specified by the commands RA and Rb fields.
Execute: If the ALU executes the operation specified by the instruction, calculate the valid address referenced by the memory, or increase or decrease the stack pointer, the value obtained is Vale. For the jump instruction, this stage checks the condition codes and branch conditions.
Memory Access: data can be written to or read from the memory. Set to valm.
Write back: Up to two results can be written to the register file.
Update: Set the PC address to the address of the next command.

· The process required to execute a command: The operation indicated by the execution command, the calculation address, the updated Stack pointer, and the address of the next command are determined.

· Processing of three transfer control commands: Pay attention to the bit signal CND. In the update PC phase, check this flag. If this flag is 1, set the PC to valc (jump to the target). If it is 0, set it to valp (the address of the next command ).

 

·SEQ schematic drawing practices:

The light gray box indicates the hardware unit.
The control logic block is represented by a gray rounded rectangle.
The line name is described in white elliptic
Data connections with a font width are represented by a line of moderate width.
Bytes in width or narrower data connections are represented by thin lines.
The connections of a single bit are represented by dotted lines.

 

Processor principle: the processor never needs to read the updated state of the instruction to complete the execution of an instruction.

 

· Seq stage implementation

· NOP command: no processing is performed except adding 1 to the PC;
· Halt command: sets the processor status to HLT, causing the processor to stop running.

Address retrieval stage -- Decoding and writing back stage -- execution stage -- Memory Access stage -- Update PC stage

 

20145222 Summary of the sixth week of information security system design (1)