2015.4.5 Random access memory

random access memory is divided into two types, static ( S) and dynamic (D), Static (SRAM) is much faster than dynamic (DRAM) because SRAM as Cache , DRAM as a frame buffer for main memory and graphics system .

1. static RAM

Each data bit of SRAM exists in a bistable storage unit (bistable: Only two stable equilibrium states, note, not only balance, but also to stabilize the balance, means that a little bit of interference will not change the state, if in an unstable state, it will be converted to stable state), so as long as there is electricity, The data will never change.

2. Dynamic RAM

DRAM uses capacitors to hold data bits, so the stability of the voltage represents the degree of stability of the data bits. It is because of the differences in the physical structure that the DRAM and SRAM occupy a different space, the materials used are different, the price is different, the degree of stability is also different.

Because it is a capacitor, it will be leakage from time to time, it will need to refresh from time to time. Of course, error correction codes can also be used to correct the wrong bits.

The physical structure of SRAM and DRAM leads to the size of the space, the degree of stability of the data storage, and the market price.

3. Traditional DRAM

All the bits in the DRAM are divided into hyper-units, which is what we commonly say (bytes). Divided into a small unit, and then through the rectangular arrangement of these small units, so that the data used by the small unit, the required pin will be less (pin: a PIN can transmit a data, the pin is to transmit the address), After the address is transmitted through the PIN, we can read the data from the DRAM chip.

How to read the data in the chip? Each DRAM chip connected to the storage controller , this circuit can transfer the address to the chip, respectively, the RAS and CAS, which is the line number and the column number, because the matrix of the data chip, the row number is determined after the column number, we can only determine a super-unit.

Of course, the line number and the column number of the transmission is a time difference, first, so, after the incoming line number, we put a line of data in the chip is copied to the chip inside the row buffer , and then read the data in that column's superclass from the inner row buffer.

4. Memory Module

For a word, because the composition of the bytes belong to a single unit, so distributed on different chips, so when I transfer, I need to give different chips in the same coordinates, get a word of different bytes of data, and then merge, before you can obtain the word data.

Each byte in this word is obtained from the internal line buffer in the chip, while merging the actual storage controller.

5. Enhanced DRAM

In the original DRAM structure, we can see that the efficiency is slightly lower, so we can make many improvements.

The first improvement of the fast-page mode dram (Fast dram,fpm DRAM) is that I want to read the data on a single line in the chip (which is very likely based on spatial locality), and I don't have to copy the data into the internal row buffer every time, but I can get it directly from the buffer.

Extended Data output dram (extenged data out Dram,edo DRAM). is an enhanced drive for FPM DRAM, allowing the CAS signal to be more tightly

Synchronous DRAM (Synchronous Dram,sdram), with the storage controller using the same clock signal, the details are not discussed, in short, faster.

Double Data rate synchronous DRAM (double data-rate synchronous dram,ddr DRAM) is an enhancement to SDRAM, which uses two clock edges as the control signal, doubling the reading speed.

Evolutionary process: FPM Dram-edo Dram-sdram and DDR SDRAM

6. non-volatile line memory

If power is lost, Ram loses data, ROM can save data.

A ROM that a prom can turn into once

EPROM (erase) erasable programmable rom

Flash non-volatile, EPROM-based, fast and durable non-momentary storage, based on flash memory to invent a solid state drive.

program stored in ROM becomes firmware (firmware)

7. Accessing main memory

Data, address, instruction and so on through the bus to transmit, the bus according to data, address and instructions are divided into the bus, address bus, instruction bus. The instruction bus carries the instruction, the data bus carries the information, address bus carries the address.

Between the CPU and the I/O bridge is connected via the system bus, the I/O bridge and the garrison are connected by the memory bus. Now brother computer system design innocent bus has different design. But the three buses work together, the instructions decide what to do, the address determines where to do, the data determines what to do, the three coordinate with each other, can access the main memory from the CPU or store the data to main memory.

2015.4.5 Random access memory