2018-2019-1 20165221 summary of the fifth week of Information Security System Design Basics

1. Storage Technology
Volatile memory

SRAM and DRAM

Traditional DRAM and enhanced dram
Traditional dram

① The Unit (BIT) in a dram chip is divided into D super units, each of which is composed of w dram units, and a D x w dram stores DW bit information. The supercell is organized into a rectangular array of column C in the r row, Rc = D. The address of each supercell is expressed by (I, j) (starting from scratch ). A two-dimensional matrix is designed to reduce the number of address pins on the chip.

② Information is sent to the chip through an external connector called a pin, each carrying a one-bit signal.

③ Each DRAM signal is connected to a circuit called a storage controller, and each transmission of the circuit is 8 bits. Row address I, Ras request; column address J, CA

④ Share the same DRAM address pin. One reason for organizing a two-dimensional array instead of a linear array is to reduce the number of address pins on the chip. The disadvantage of two-dimensional array blocking is that the address must be sent in two steps, which increases the access time.

Enhanced dram

Fast-page mode DRAM (FPM Dram): asynchronous control signal that allows continuous access to the same row to get services directly from the row buffer.

Extended Data Output DRAM (Edo Dram): asynchronous control signal that allows Separate CAS signals to be more time-intensive

Synchronous DRAM (SDRAM): synchronous control signal, faster than asynchronous

Double Data Rate synchronization DRAM (ddr sdram): uses two clock edges as the control signal to double the dram speed.

Rambus DRAM (RDRAM): A private Technology

Video RAM (VRAM): Used in the frame buffer of the Graphic System.

Memory Module
Dual-row direct-insertion memory module (dimm): 168 pins, with 64-bit incoming/outgoing data to the storage controller.
Single-Column Direct Memory Module (SIMM): 72 pins, 32-bit for incoming/outgoing data to the storage controller.
Access primary storage
Read transaction: transfers data from primary storage to cpu
Write transaction: transfers data from CPU to primary storage
Bus: A group of parallel wires that can carry addresses, data, and control signals.
System Bus: Connection bus interface and I/O bridge
Memory Bus: connected to the I/O bridge and primary storage
Non-volatile memory

Rom (read-only memory)
ROM can be categorized by the number of times they can be reprogrammed and the mechanisms used to reprogram them: Prom (Programmable ROM), EPROM (Erasable Programmable ROM ), flash Memory (based on EEPROM), solid state drive (SSD, based on flash)
Disk
Disk Structure

Disk operations: Seek, rotate, and read (time overhead is mainly caused by seek time and rotation delay)

Logical Disk block: there is a small hardware/firmware device in the disk, which is called a blank disk. It maintains the ing between the logical block number and the actual physical disk sector.
SSD)
Solid State Disk Structure: The Flash Translation Layer works the same as the disk controller. A flash memory consists of B block sequences, and each block consists of P pages.
Data is read and written in units of pages. This page can be written only after the entire block to which a page belongs is erased (valid content is copied to other blocks. Generally, the page size is 512 ~ 4 kb, the block is from 32 ~ Page 1.
2. Limitations
(1) temporal locality: memory locations that have been referenced once may be referenced multiple times in the near future.

(2) spatial locality: data near a referenced memory location may be referenced in the near future.

(3) Take the locality of the command: The command is also stored in the memory, and the cycle time and space locality are good. The smaller the loop body, the more iterations, the better the locality.

3. Memory Hierarchy
Cache in the Memory Hierarchy

The high-speed cache determines whether a request is hit, and then extracts the requested word, the process is divided into three steps
Group selection
Row match
Word Extraction
When the cache does not hit a direct ing, each group contains only one row. The replacement policy is to replace the current row with the row retrieved with your heart.
A 1 <e <C/B notification cache is usually called an e-path group-connected high-speed cache.
Memory Hierarchy

4. High-speed cache storage
General high-speed cache memory structure

In a computer system, each storage address has m bits, forming m = 2 ^ m different addresses.
The cache is organized into an array with S = 2 ^ s cache groups. Each group contains e cache rows, each row is composed of-a data block of B = 2 ^ B bytes, a valid bit, and t = m-(B + S) tags, uniquely identifies the block stored in this cache row.
The cache structure is described by tuples (S, E, B, m). The cache size is c = S * E * B.
Direct ing to high-speed cache

Direct ing of High-speed cache: each group has only one row of High-speed cache.
Group selection:
The cache extracts S group index bits from W's address.
Group Index bit: an unsigned integer corresponding to a group number.
Line Match:
Two necessary conditions for determining cache hits: the row sets a valid bit; the mark in the cache row matches the mark in the W address.
Word selection: determines where the desired word starts in the block.
Group-connected high-speed cache

Group selection in the group connected to the high-speed cache: The same as the group selection in the direct ing high-speed cache, the group index bit Identification Group.
Row matching and word selection in group-connected high-speed cache: each group is considered as a small memory associated with each other, and is an array of (Key, value) pairs,
Return the value of the corresponding array based on the input key. The cache must search for each row in the group to find a valid row whose flag matches the one in the address.
Line replacement when a node is not hit in the cache: the simplest replacement policy is to randomly select the row to be replaced. Other complicated policies use the Locality Principle, for example, least frequently used and least recently used.
Fully-connected high-speed cache

Select a group in the all-connected high-speed cache: there is only one group with no group index bits.
Row matching and word selection in a fully-connected high-speed cache: the high-speed cache is the same as that in a group, but it is large in size. Therefore, it is only suitable for small high-speed caches, for example, the translation backup buffer in the virtual storage system.
Write Problems

Direct write:
Immediately write W's high-speed cache block back to the next layer
The disadvantage is that each write will cause bus traffic.
Write back:
Only when the replacement algorithm needs to evict the updated block can it be written to the next lower layer. Due to locality, writing back can significantly reduce bus traffic.
The disadvantage is increased complexity.
Another problem is how to deal with write Miss.
Write allocation: load the corresponding lower-level block to the cache, and then update the cache block. The disadvantage is that each Miss will cause a block to be transferred from the lower layer to the cache.
Non-write allocation: Avoid high-speed caching and write the word directly to the lower layer.
Performance impact of high-speed cache Parameters

Hit rate: No hits/reference quantity
Hit rate: 1-no hit rate
Hit time: the time required to transfer a word from the cache to the CPU, including the group selection, row matching, and word extraction time.
Penalty for Miss: the extra time required for Miss.
Overall: the impact of high-speed cache on Program Performance

Storage Hill
The speed at which a program reads data from the storage system is called the read throughput or read bandwidth, usually measured in megabytes per second (MB/s.
Two-dimensional functions of read bandwidth Time and Space locality are called memory mountains.

2018-2019-1 20165221 summary of the fifth week of Information Security System Design Basics