2018-2019-1 20165225 "Information Security system Design Fundamentals" Fourth Week study summary

Fourth Chapter processor Architecture

Programmer Visible State

Each instruction in the Y86 program reads or modifies portions of the processor state, called the programmer's visible state. These include:

8 Program Registers:%eax,%ecx,%edx,%ebx,%esi,%edi,%esp and%EBP.

Condition code: ZF (0), SF (symbol), of (signed overflow)

Program Counter (PC): Stores the address of the currently executing instruction

Memory: A large array of bytes that holds programs and data. The Y86 system uses virtual addresses to refer to the location of the memory, and the hardware and operating system software are combined to translate the virtual address into a physical or an actual address.

Status code (STAT): Indicates the overall state of the program's execution.

Logic design and hardware control Language HCL
The output generated by the logic gates is a Boolean function that equals their input bit values.
&&
OR | |
Not!
The logic gate operates only on the number of individual bits, not the entire word.
Combinational Circuits and HCl Boolean expressions
Combination of Word-level circuits and HCl integer expressions
In the processor design, it is often necessary to compare a signal to a number of possible matching signals to detect if a certain instruction code being processed is part of a class of instruction code.

Sequential implementation of Y86-64
Organize the processing into stages
1. For OPL (integer and logical Operations), RRMOVL (register-register transfer) and IRMOVL (immediate count-register transfer)
2. For RMMOVL and Mrmov
3. For PUSHL and POPL
4. For jump, call and RET
Take a finger
Decoding
Perform
Visit
Write back
Update pc
Timing Control: Program counter, Condition code register, data register, register file.

2018-2019-1 20165225 "Information Security system Design Fundamentals" Fourth Week study summary