2018-2019-1 20165321 summary of the fifth week of Information Security System Design Basics

Summary of teaching material learning content

• Random Access to memory
  -- SRAM stores each bit in a bistability memory unit. As long as there is electricity, it will keep its value forever.
  -- DRAM stores each bit as a charge for a capacitor, and the memory system must periodically read it and then rewrite it to refresh each bit in the memory.
  -- Characteristics of SRAM and DRAM memory.
  
• In traditional dram, units (BITs) in DRAM are divided into D superunits, which are organized into a rectangular array with R rows and C columns. Information is sent to the chip through an external connector called a pin. Each pin carries a one-bit signal. Each DRAM signal is connected to a circuit called a storage controller, and each transmission of the circuit is 8 bits. Row address I, Ras request; column address J, CAS request.
• Enhanced dram
  -- Fast page mode: allows continuous access to the same row to directly obtain services from the row buffer.
  -- Extended data output. CAS signals depend more closely on time.
  -- Synchronous: communicates with the memory controller using a set of explicit control signals.
  -- Double data rate synchronization, using two clock edges as the control signal.
  -- Video RAM is used in the frame buffer of the Graphic System. The output is obtained by shifting the entire content of the internal buffer in sequence, and parallel read and write operations on the memory are allowed.
• Non-volatile memory, which stores information after power failure.
  -- Prom, which can only be programmed once.
  -- EPROM: the uv is cleared, and the number of rewrites reaches 1000.
  -- EEPROM: the specified voltage can be erased, and the number of times it is programmed reaches 100000.
  -- Flash memory, including solid state disks.
• Access primary storage
  -- Read the transaction and transmit data from the primary memory to the CPU.
  -- Write a transaction to transfer data from the CPU to the primary storage.
  -- Bus, a group of parallel wires that can carry addresses, data, and control signals.
  -- System bus, connection bus interface and I/O bridge.
  -- Memory bus, connected to the I/O bridge and primary storage.
• The bus is divided into address bus, data bus, and control bus by content.
• Disk
  -- Disks> channels> sectors. Each sector contains an equal number of data bits.
  
• The disk reads and writes data in blocks of the sector size.
• Connect to an I/O device, PCI Bus (Intel ).
• SSD
  -- SSD Structure: The Flash Translation Layer works the same as the disk controller. A flash memory consists of B block sequences, and each block consists of P pages.
  -- Data is read and written on pages. This page can be written only after the entire block to which a page belongs is erased (valid content is copied to other blocks. Generally, the page size is 512 ~ 4 kb, blocks from 32 ~ Page 1.
• Locality, tends to reference data items that are adjacent to other recently referenced data items, or reference the recently referenced data items themselves (The step size is as small as possible ).
• Memory hierarchies. For each K, a faster and smaller storage device located on the K layer is used as the cache for a larger and slower storage device located on the K + 1 layer. Each layer in the hierarchy caches data objects from the lower layer.
• Memory Hierarchy:
  
• Cache hit: Find data at the K + 1 layer and find it in the cache content at the K layer. You can directly read data at the K layer, which is called cache hit.
• Cache miss. No data is found at the K layer. The cache at the K layer needs to retrieve the block containing objects from the cache at the K + 1 layer. If the K layer is full, overwrite an existing block. Cool hit, the K layer has nothing, so it does not hit.

• High-speed cache memory, mainly the size (p426) and probability (p431)
  

  Summary of test errors last week

2018-2019-1 20165321 summary of the fifth week of Information Security System Design Basics