2018-2019-1 20165330 "Information Security system Design Fundamentals" Fourth Week study summary

Learning content Summarizing learning objectives

1. Understanding the role of ISA abstraction
2. Master Isa, and be able to learn other architecture extrapolate

Learning content

Y86-64 directive

2. Programmer Visible Status
   • 15 program Registers (RF): Each register stores a 64-bit word
     
   • 3 Conditional codes (CC): Save information about the impact of the most recent arithmetic or logic directives
     • ZF: 0 Flag (The result of the operation is 0 zf=1; The result is not 0 zf=0)
     • SF: Symbol flag (the highest result is 0 sf=0; The result is the highest bit is 1 sf=1)
     • of: Overflow flag (no overflow of=0 for signed results, result overflow calculation error of=1)
   • program Status (Stat)

   value	name	meaning
   1	AOK	normal operation
   2	HL T	encountered executing halt directive
   3	ADR	encountered illegal address
   4	INS	encountered illegal instruction

   • program counter (PC ): The address of the current instruction
   • memory (DMEM): is a large array of bytes, storing programs or data
4. Y86-64 directive
   • Y86-64 Program Register Identifier
     • stored in a register file on the CPU
     • No registers should be accessed: denoted by 0xF
   • Y86-64 instruction Encoding
     • Encoding Length: 1 bytes ~ byte
     • Code composition: 一个单字节的指令指示符 + 一个单字节的寄存器指示符 +一个八字节的常数字
     • Integer operation instruction OPq : addq subq andqxorq
     • Jump command jXX jmp jle jl : je jne jgejg
     • Delivery Instructions comvXX comvle comvl comove : cmovne cmovgecomovq
     • field FN (function code) indicates an integer operation, data transfer condition, or branch condition
       

Logic design and hardware control Language HCL

1. HCL expression
   • and && , or || , not!
   • And, or, not three kinds of logic gates can be implemented with a non-gate or non-gate
2. HCL integer Expression
   • Case Expression Format:

     [     select 1: expr 1     select 2: expr 2     .     select k: expr k  ]

   • Set Relationship:iexp in{ iexp1,iexp2,...iexpk }
   • Arithmetic/logic unit (ALU)
     

Sequential implementation of Y86-64

1. Organize the processing into stages
   • Value fetch--> decoding decode--> performing execute--> memory--> writeback write back write back--> update PC update

2. SEQ Hardware structure
   

   • The white box indicates the clock register
   • A light blue box indicates a hardware unit
   • Gray rounded rectangles represent control logic blocks
   • The name of the line in the white circle
   • Medium thick lines indicate a data connection with a width of length
   • A thin line represents a data connection with a width of bytes or narrower
   • Dashed lines represent a single bit of a connection

2018-2019-1 20165330 "Information Security system Design Fundamentals" Fourth Week study summary