2018-2019-1 20165336 "Information Security system Design Fundamentals" Fourth week study summary 1. The knowledge points learned in the textbook
- The states that are visible to programmers (assembler programmers, compilers, and so on) in y86-64 include program registers, condition codes, program states, program counters (PCS), memory
- Y86-64 15 Program registers are%eax%ecx%edx%ebx%esp%ebp%esi%eadi ZF SF of PC Stat DMEM
- The length of the integer operation supported by the y86-64 instruction is 8 bytes
- The instruction encoding length of the y86-64 is 1-10 bytes, and the instruction encoding length varies from 1-6 bytes. An instruction contains a single-byte instruction designator, which may contain a single-byte register designator, and may contain a four-byte constant number
- Y86-64 has 7 jump instructions for JMP, Jle, JL, je, jne, Jge, and JG.
- Y86-64 Status Code AOK indicates normal operation, 3 indicates an illegal address encountered, HLT processor executes halt command, ADR encounters illegal address, INS encounters illegal instruction
- Implementing a digital system requires three main components: the combination logic that computes the function that operates on the bit, the memory element that stores the bits, and the clock signal that controls the update of the memory element.
And, or, not three kinds of logic gates can be implemented with a gate (with a non-gate, or not gate).
- Multiplexer. The multiplexer selects one from a different set of data signals based on the value of the input control signal.
- The ALU is a combinational circuit, and a register is a sequential circuit that distinguishes between having no clock.
- Each time the clock reaches the top edge, the value is transferred from the register input to the output. Our Y86 processor stores the program counter (PC), Condition Code (CC), and program status (STAT) with a clock register.
- The register file has two read ports and a write port. Such a multi-port random access memory allows multiple read and write operations at the same time. Writing a word to a register file is controlled by a clock signal.
- y86-64, instruction execution is divided into 6 stages fetch, decode (decode), execute (Execute), memory, write back (write), update PC (PC update)
- During the execution phase, the arithmetic/logic unit (ALU) either executes the operation specified by the instruction (according to the value of Ifun), calculates the valid address of the memory reference, or increases or decreases the stack pointer. The value we get is called Vale. In this case, the condition code may also be set. For a jump instruction, this phase examines the condition code and branching conditions to see if the branch should be selected.
- The RRMOVL is a register-register transfer, IRMOVQ is an immediate count-register transfer, which does not require an inbound memory.
In seq+, a status register is created to hold the signal computed during the execution of an instruction. Then, when a new clock cycle starts, these signal values pass the same logic to calculate the current instruction of the PC.
The change of the state element in the seq+ is called Circuit retiming, and the pipeline registers are inserted between the stages of the seq+ and the signals are rearranged.
Problems in teaching materials learning and solving the problems in the process book instruction coding problem: need to master y86-64 instruction set, y86-64 instruction set function code, y86-64 program Register identifier
Summary of wrong questions in exams
- 1.4. In y86-64, for a jump instruction, decide whether the stage to which the branch should be selected is ()
A. Fetch
B. Decode
C. Execute
D. Memory
E. Write back
F. PC Update
Correct answer: C
parsing: During the execution phase, the arithmetic/logic unit (ALU) either executes the operation specified by the instruction (according to the value of Ifun), calculates the valid address of the memory reference, or increases or decreases the stack pointer. The value we get is called Vale. In this case, the condition code may also be set. For a jump instruction, this phase examines the condition code and branching conditions to see if the branch should be selected.
- 2. The code in the figure illustrates the details of the exception handling problem is ()
A. Simultaneous multiple instructions cause an exception
B. Instruction execution causes an exception, and later, due to branch prediction errors, the instruction is canceled
C. Different parts of the system state are updated at different stages
D. Pipeline-Independent exceptions
Correct answer: B
parsing: In this program, the pipeline predicts the selection branch, so he takes out and takes a byte with a value of 0xFF as the instruction. The decoding phase will therefore find an illegal instruction exception. Later, the pipeline will find that the branch should not be selected, so you should not remove the instruction at address 0x00e at all. The pipelined control logic cancels the instruction, but we want to avoid exceptions.
2018-2019-1 20165336 "Information Security system Design Fundamentals" Fourth Week study summary
