2018-2019-1 20165306 summary of the fifth week of Information Security System Design Basics

2018-2019-1 20165306 "Information Security System Design Basics" week 5 study summary teaching material Learning Content summary 6.1 storage technology 6.1.1 random access storage

• Static RAM (SRAM): A bi-stable feature that maintains its value as long as it has electricity. Even if there is interference to disturb the voltage, when the interference is eliminated, the circuit will return to the stable value.

• Dynamic RAM (Dram): When the voltage of a capacitor is disrupted, it will never be restored.

• Traditional DRAM: the row address I is called a RAS request, and the column address J is called a CAS request. Note that the RAS and CAS requests share the same DRAM address pin.

• Enhanced dram
  • Ftp dram (fast page mode): allows continuous access to the same row to get services directly from the row buffer.
  • Edo DRAM (extended data output): allows CAS signals to be more time-intensive.
  • SDRAM (synchronous): faster.
  • Ddr sram (double data rate): uses two clock edges as control signals to double DRAM speed.
  • VRAM (video): Used in the frame buffer of the Graphic System.
• Non-volatile memory
  • Prom (Programmable): can only be programmed once; EPROM (Erasable Programmable): 1000; EEPROM (Electronic erasable): 10 ^ 5 times.
  • Flash Memory: a flash-Based Disk Drive is called an SSD (solid state drive), which is faster, more robust, and more energy-consuming.

• Firmware: programs stored on ROM devices.

• A bus is a set of parallel wires that can carry addresses, data, and control signals.

6.1.2 disk storage

• Disk structure:
  -A disk consists of disks. Each disk has two surfaces.
  -Generally, the conversion speed is 5400-15000 per minute (RPM ).
  -Each surface is composed of a group of concentric circles called magnetic channels.
  -Each track is divided into a group of sectors. Each sector contains an equal number of data bits (usually 512 bytes ).
  -The Gap storage is used to identify the formatting bit of the slice.
  -The cylinder is a collection of tracks with the same distance from the disc surface to the center of the spindle.

• The disk reads and writes data in blocks of the sector size. The average time for accessing the content of a disk sector is the sum of the average seek time, average rotation delay, and average transfer time.
  -The 512-byte access time in a disk sector is mainly the seek time and rotation delay.
  -Multiplying the seek time by 2 is a simple and reasonable way to estimate the disk access time.

6.2 locality

• Locality Principle: reference data items that are near other recently referenced data items, or recently referenced data items themselves.

• The reference mode with Step 1 is sequential reference mode. Generally, as the step size increases, the space locality decreases.

• The commands in the loop body are executed in a sequential memory, so the loop has a good spatial locality. Because the loop experience is executed multiple times, it also has a good time locality.

• The program that repeatedly references the same variable has a good time locality. The smaller the step size, the better the local space.

6.3 storage hierarchy

• The central idea of the storage hierarchy: a faster and smaller storage device located on the K layer serves as the cache for larger and slower storage devices located on the K + 1 layer.
• Data is always replicated back and forth between layer K and layer k + 1 Based on the block size. Although the block size of any pair of adjacent layers in the hierarchy is fixed, other levels can have different block sizes.
• Cache hits: Cold cache (mandatory or cold hits); conflict hits; Capacity hits.
• The essence of the Memory Hierarchy: each layer of storage devices is a lower layer of cache.
• Cache-based memory hierarchies are effective because slow storage devices are cheaper, and programs tend to display locality (time and space ).

6.4 high-speed cache memory

• The cache structure divides m addresses into T tag bits, s index bits, and B block offset bits.
• (S, E, B, m) C = s × E × B

• Direct ing of High-speed cache: E = 1
  -Group selection: the cache extracts S group index bits from W's address.
  -Row match: if and only when a valid bit is set, and the mark in the cache row matches the mark in W's address, this row contains a copy of W.
  -Word selection: The Block offset provides the offset of the first byte of the required word.
  -Line replacement when a hit is not hit: Replace the current row with the new row.

6.5 write cache-friendly code

• Make the most common cases run fast.
• Minimize the number of cache hits in each loop.
• It is good to repeatedly reference local variables, and the reference mode with Step 1 is good.

6.6 integration: Impact of high-speed cache on Program Performance

• Storage Mountains: Two-dimensional functions of the time and space locality of read bandwidth. The performance of the memory system is not described by a number. On the contrary, it is a mountain of Time and Space locality, and the rising height of this mountain can be more than an order of magnitude.

• Use locality in programs:
  -Focus your attention on the internal loop;
  -Read data in step 1;
  -Once a data object is read from the memory, use it as much as possible.

Teaching material problems and solutions

• Exercise question 6.4: see Book p411. For the answer, see p459.

I don't quite understand a sentence in the parsing.This file consists of 2000 512-byte logical blocks.

• References

P409: For the measurement units related to the capacity of I/O devices such as disks and networks, K = 10 ^ 3, M = 10 ^ 6, G = 10 ^ 9, T = 10 ^ 12.

My understanding is: 1 MB = 10 ^ 6 bytes, 512 ≈ 5 × 10 ^ 2000 ^ 6/(5 × 10 ^ 2) =.

Summary of last week's exam errors

• P261 in the book: Logical Circuits can be designed to execute many different types of operations on word-level data. Arithmetic/logical unit (ALU) is a very important combination circuit.

• P262: in order to generate a time series circuit, that is, a stateful system that performs computing in this state, we must introduce a device that stores information by bit. The storage device is controlled by the same clock. The clock is a periodic signal and determines when to load the new value to the device.
  -The clock register (register for short) stores a single bit or word. The input value is loaded into the clock signal control register.
  -Random access memory (memory for short) Stores multiple words and uses the address to select the word to read or write.

2018-2019-1 20165306 summary of the fifth week of Information Security System Design Basics