2018.03.27-amba protocol (AHB APB Axi, etc.) \ Peripheral Communication protocol (SPI can, etc.)

Added the AXI4 specification (the specification for in-SOC IP interconnect developed by ARM and XILINX), with the addition of the Advanced System Bus (ASB) and advanced Peripheral Bus (APB) to the latest version of AMBA4.0, from the very beginning of the AMBA1.0 version definition to the AHB APB, the Advanced tracking bus ATB, et. The AHP APB Axi can be considered as the bus protocol or specification within the scope CPU, however we often refer to the SPI can bus for peripheral communication, which is actually the communication layer protocol of the SPI controller or the can controller and the peripheral chip. In the SPI controller can controller and CPU communication, the use of Amba Bus protocol, through the AMBA bus protocol to read or write to the SPI or can cache, and then by the SPI can start its own communication protocol, the data to the peripheral, or read the peripheral data.

AMBA APB:APB belongs to the AMBA3 protocol family, which provides a low-power interface and reduces the complexity of the interface. The APB interface is used on external devices that have low bandwidth and do not require a high-performance bus. APB is a non-pipelined interface, and all signals are related only to the rising edge of the clock. This simplifies the design process for APB external devices, which consumes at least 2 clock cycles per transmission.

Amba AHB:AHB is a new generation of AMBA buses designed to address high-performance, synchronous design requirements, and the AHB is an additional level of bus, higher than APB, for achieving high performance, high clock frequency system feature requirements. Requirements include: Burst transmission, split transactions, single-cycle bus master equipment handover, single clock along the operation, no three-state implementation, a wider data bus configuration (or a bit).

A typical Amba system includes the AHB and APB bus structures. The high performance ARM processor, connected to the APB bus via the AHB connection with high performance bias RAM, high bandwidth memory interface, DMA bus master, and then via AHB to APB Bridge. On the APB bus, the serial port, peripheral IO, keyboard, timer and other peripheral controller are hung.

AMBA AXI4:SOC The communication protocol between the internal IP cores.