21. Core initialization of the SVC mode

21. Core initialization of the SVC mode

To set the system to work with SVC privilege mode, learn from the front to know that this requires setting the CPSR program status register.

In the arm Architecture Reference manual.pdf Documentation, the 2.Programmers ' model 2.5.Program status register.

You can see the last five bits of CPSR: m[4:0], which is to set the system mode for the system to work.

The next step is to set the last five bits of CPSR to 0b10011, which is the SVC mode for setting up the system.

The idea of implementation is:

1. Get these five digits
2. Zero, use the BIC bit clear 0 instructions.
3. Place the 0,1,4 bit at 1, and use the ORR bit or instruction.

To obtain the CPSR after five bits, because is the operation CPSR/SPSR, cannot like the general register, the direct operation, needs to remove the CPSR/SPSR register value to carry on the corresponding operation. Instructions taken: Mrs. The final deposit is: MSR. This completes the modification operation.

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Modified code:

The above operation can be implemented to set the end of the CPSR 5 bits to 0b10011. Complete the setup system to work in SVC mode.

When we do these operations, we generally refer to the settings in the Uboot to operate. See how the Uboot is set up:

You can see that the uboot in OK6410 is set to 0xd3, and the 0xd3 binary:

See Uboot, also set the [6][7] bit to 1, look at the two-bit function, is set to interrupt, uboot the interrupt and the fast interrupt are closed.

Because Uboot is the eldest, so, here also changed to 0xd3,2440,6410,210 are the same operation. Last start. The code for S is:

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. text

. Global???? _start

_start:

???????? B???? Reset????????????????????????

???????? LDR???? PC, _undefined_instruction????

???????? LDR???? PC, _software_interrupt????????

???????? LDR???? PC, _prefetch_abort????????????

???????? LDR???? PC, _data_abort????????????????

???????? LDR???? PC, _not_used????????????????

???????? LDR???? PC, _IRQ????????????????????

???????? LDR???? PC, _fiq

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_undefined_instruction:. Word undefined_instruction

_software_interrupt:????. Word software_interrupt

_prefetch_abort:????. Word prefetch_abort

_data_abort:????????. Word data_abort

_not_used:????????. Word not_used

_IRQ:????????????. Word IRQ

_fiq:????????????. Word Fiq????????????????????

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Undefined_instruction:

???????? Nop

Software_interrupt:

???????? Nop

Prefetch_abort:

???????? Nop

Data_abort:

???????? Nop

Not_used:

???????? Nop

Irq:

???????? Nop

Fiq

???????? Nop

Reset

???????? BL Set_svc

SET_SVC:

???????? Mrs R1,CPSR

???????? BIC R1, #0x1f @clear the latter five bits of R1,

???????????????????????? @ that is, clear the CPSR after five bits

???????? Orr R1,r1, #0xd3 @0b10011=0x13

???????? MSR CPSR,R1

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21. Core initialization of the SVC mode