2440 principle of memory initialization (followed by the previous article)

Jlink debugging and loading execution initialization memory script (2440) Setmem 0x53000000 0x00000000 32 Setmem 0x4a000008 0 xffffffff 32 Setmem 0x4a00001c 0x000007ff 32 Setmem 0x53000000 0x00000000 32 Setmem 0x56000050 0x000055aa 32 Setmem 0x4c000014 0x00000007 32 Setmem 0x4c000000 0x00ffffff 32 Setmem 0x4c000004 0x00061012 32 Setmem 0x4c000008 0x00040042 32 Setmem 0x48000000 0x22111120 32 Setmem 0x48000004 0x00002f50 32 Setmem 0x48000008 0x00000700 32 Setmem 0x4800000c 0x00000700 32 Setmem 0x48000010 0x00000700 32 Setmem 0x48000014 0x00000700 32 Setmem 0x48000018 0x0007fffc 32 Setmem 0x481_1c 0x00018005 32 Setmem 0x48000020 0x00018005 32 Setmem 0x48000024 0x008e0459 32 Setmem 0x48000028 0x00000032 32 Setmem 0x481_2c 0x00000030 32 Setmem 0x48000030 0x00000030 32 Principle: 1. What is a storage controller? A storage controller is a device that creates and controls other storage devices. The starting address of the storage controller in S3C2440 is 0x48000000 and the ending address is 0x48000030. By configuring the storage controller13 registersTo access the peripheral device. 2. How to obtain the access address of the Peripheral Device Before obtaining the peripheral device address, describe what is the chip selection signal. Comrades who have read the microcomputer principles should be very clear. In S3C2440, it is divided into ngcs0 ~ Ngcs7, a total of 8 chip selection signals. Corresponding to bank0 ~ Bank7: When you need to access the space of the peripheral device (that is, when you access bankx), The ngcsx pin outputs a low-level signal, so that you can select the corresponding bankx peripheral device for access. (Note: ngcs0 ~ Ngcs7 can find the correspondingAddress Allocation Table) Bank access address = Bank start address + address line address. 3. Use of registers in the storage controller 3.1. 13 registers provided by the storage controller Bwscon,Bankconx(X = 0 ~ 7 ),Refresh,Banksize,Mrsrbx(X = 6 ~ 7 ),A total of 13 registers. In the configuration of these registers, when bank0 ~ In bank5, you only need to configure bwscon and bankconx (x = 0 ~ 5. Because bank6 and bank7 have two orders of DRAM, in addition to bwscon and bankconx (x = 6 ~ 7) you also need to configure four registers, including refresh, banksize, mrsrb6, and mrsrb7. Bwscon(R/WBUsWIdth & WaitSTatusConTrol, Bit Width and wait register) Bwscon has 32 bits. The 4 bwscon high bits correspond to the bank7 of the peripherals. However, bwscon corresponds to a bank for every 4 bits, so the rest of the bank6 can be obtained in turn ~ The number of digits corresponding to bank0. STX (x = 0 ~ 7): Start/disable the SDRAM data mask pin. For SDRAM, this bit is 0, and for SRAM, this bit is 1. It is generally 0. Wsx (x = 0 ~ 7): whether to use the memory's wait signal. It is usually set to 0. /* 0 = wait disable */ Dwx (x = 0 ~ 7): use 2 bits to set the corresponding bank bits (data bus width), 00 = 8-bit; 01 = 16-bit; 10 = 32-bit; 11 = Reserved Where,Special bank0, It does not have st0 and ws0, and dw0 [2:1] is read-only, determined by the hardware circuit jumper 01 = 16-bit; 10 = 32-bit. Bankconx (x = 0 ~ 5 ):Used to control the access time sequence of external devices. It is set by default.Zero X 0700It can meet your needs. Bankconx (x = 6 ~ 7 ):Only bank6 and bank7 can be used for external access to SRAM or SDRAM. Therefore, when configuring bank6 ~ Bank7 may be different. MT [16: 15] Bits: used to identify whether the external device is rom/SRAM or SDRAM. /* 00 = Rom or SRAM; 01 = reserved; 10 = reserved; 11 = Sync.DRAM */ When MT = 0b00 (external ROM ):Bankconx (x = 0 ~ 5)There is no big difference. When MT = 0b11 (external SDRAM ): Trcd [3: 2]:TIME OfRAsCAsDElay) /* 00 = 2 clocks; 01 = 3 clocks; 10 = 4 clocks */ Scan [1:0]: The address of the SDRAM column. You can set it to/* 00 = 8-bit; 01 = 9-bit; 10 = 10-bit */ Refresh: refresh the control register. Refen [23]: Enables control of the sdram refresh function. /* 0 = Disable; 1 = Enable (self or CBR/auto refresh )*/ Trefmd [22]: SDRAM refresh mode. /* 0 = CBR/auto refresh; 1 = self refresh (sleep mode )*/ TRP []:TIME Of SDRAMRAsPRe-charge (RAS pre-charging time ). /* 00 = 2 clocks; 01 = 3 clocks; 10 = 4 clocks; 11 = not support */ Tsrc [19: 18]:TIME Of SDRAMSEmiROwCYCLE (half-row cycle time ). /* 00 = 4 clocks; 01 = 5 clocks; 10 = 6 clocks; 11 = 7 clocks */Note: Reserved [17: 11]: Not used. Refresh counter [10: 0]: SDRAM refresh Count value (refresh Count value ). Banksize register: Burst_en [7]: ARM coreBurst Operation enable (enable for core burst operations in arm ). /* 0 = Disable burst operation; 1 = Enable burst operation */Note: Reserved [6]: Not Used. Scke_en [5]: SDRAM power down mode enable controlScke. (Scke Power down mode)/* 0 = SDRAM power down mode disable; 1 = SDRAM power down mode enable */ Sclk_en [4]: Sclk is enabled only during SDRAM access cycle for logging cing power consumption. When SDRAM is not accessed sclk becomes 'l' level (low level ). /* 0 = sclk is always active. 1 = sclk is active only during the access (recommended ). */Note: Reserved [3]: Not Used. Bk76map [2: 0]: Set bank6 ~ The size of bank7. /* 010 = 128 MB/128 MB; 001 = 64 MB/64 MB; 000 = 32 M/32 m; 111 = 16 m/16 m; 110 = 8 m/8 m; 101 = 4 M/4 m; 100 = 2 m/2 M */ Mrsrbx (x = 6 ~ 7): registers are set in the SDRAM mode. Only cl [6: 4]: Parameters that represent the time series of SDRAM. /* 000 = 1 clock; 010 = 2 clocks; 011 = 3 clocks; others: Reserved */

 

 

 

 

2410 introduction to memory controller (bwscon)

Http://blogold.chinaunix.net/u1/59572/showart_1914422.html

 

 

The following is an overview of the basic features of the memory controller:   -Little/big endian (selectable by a software) -Address Space: 128 Mbytes per bank (total 1 GB/8 banks) -Programmable access size (8/16/32-bit) for all banks blocks t bank0 (16/32-bit) -Total 8 memory banks Six memory banks for Rom, SRAM, etc. Remaining two memory banks for Rom, SRAM, SDRAM, etc. -Seven fixed memory bank start address -One flexible memory bank start address and programmable bank size -Programmable access cycles for all memory banks -External wait to extend the bus cycles Supporting self-refresh and power down mode in SDRAM The size of bank6 and bank7 must be the same, and the starting address of bank7 varies according to the size of bank6.   The memory ing diagram of S3C2410A After resetting is as follows:     The width of bank0 (ngcs0) Data Bus is determined by OM [1:0: Om [1:0] = 00 NAND flash mode 01 16-bit 10 32-bit 11 Test Mode 2) Take figure 2 (with nwait signal) as an example to describe the read operation process of the processor's bus to describe the overall read and write processes of flash. At the beginning of the first clock cycle, the system address bus provides the address of the bucket to be accessed. After the TACs time, the chip selection signal is also provided accordingly (the online address information of the current address is locked ), after the tcso time, the processor will show whether the current operation is read (NOE is low) or write (New is low), and prepare the data on the bus within the tacc time, after the tacc time (and view the nwait signal, if it is low, the current bus is extended to Y for a clock cycle), NOE is increased, and data from the data line is locked. Such a bus operation is basically complete     Figure 2 bus read operations with nwait Signals     Related registers Data width and wait control register: BwsconIP address 0x48000000 Bwscon is a group of four digits, controlling bank0 to bank7. Taking bank7 as an example, the four digits are: st7 [31], ws7 [30], dw7 [] St7: Start/disable the data mask pin of the SDRAM. For the SDRAM, this bit is 0; For the SRAM, this bit is 1. Determine SRAM for using UB/LB for bank 7. 0 = not using UB/lb (the pins are dedicated nwbe [3: 0]) 1 = Using UB/lb (the pins are dedicated NBE [3: 0]) NBE [3:0] is the 'and 'signal nwbe [3:0] And noe. Ws7: whether to use the memory's wait signal, usually set to 0 Dw7: Use two digits to set the memory Bit Width:-8 bits,-16 bits, 10-32 bits, and 11-retained. Similar to this, other banks have four digits corresponding to bank0, which are determined by the hardware jumper and read-only.   Bank control register (bankconn: nGCS0-nGCS5): reset value: 0x0700 Bankcon0IP address 0x48000004 Bankcon1IP address 0x48000008 Bankcon2Address 0x4800000c Bankcon3IP address 0x48000010 Bankcon4IP address 0x48000014 Bankcon5IP address 0x48000018 Bank control register (bankconn: nGCS6-nGCS7): reset value: 0x0700 Bankcon6Address 0x481_1c Bankcon7IP address 0x48000020   Each bank control register only uses [] bits, mainly to control the size of each parameter in the read/write sequence, such as TACs and TCOs. For bank6 and bank7, use [] to control the storage mode of bank6 and bank7. 00 indicates using ROM or SRAM storage, and 11 indicates using SDRAM storage.   This development board uses two pieces of memory with 32 Mbyte and 16 Bit Width to form a memory with 64 Mbyte and 32 bit width. Therefore, the bwscon corresponding bit is 0010. For this development board, bwscon can be set to 0x22111110: in fact, we only need to set the four bits corresponding to bank6 to 0010. The other values have no effect, this value is provided in the reference manual. 2. BANKCON0-BANKCON5: we are useless, use the default 0x00000700 3. BANKCON6-BANKCON7: set to 0x00018005 Of the eight banks, only bank6 and bank7 can use SRAM or SDRAM, so BANKCON6-7 is a little different from BANKCON0-5: A. MT ([16: 15]): used to set the outside of the bank is SRAM or SDRAM: SRAM-0b00, SDRAM-0b11 B. When MT = 0b11, you also need to set two parameters: Trcd ([3: 2]): Ras to CAS delay, set as recommendation value 0b01 Scan ([1:0]): The column address bits of SDRAM, for this development board uses the SDRAM HY57V561620CT-H, column address bits is 9, so scan = 0b01. If you use another type of SDRAM, you need to check its Data Manual to determine the scan value:-8 bits,-9 bits, 10-10 bits   Refresh control register: RefreshAddress: x4821324 Refresh (SDRAM refresh control register): Set to 0x008e0000 + r_cnt Address 0, where r_cnt is used to control the update cycle of the SDRAM, occupying the [] bit of the refresh register. Its value can be calculated as follows (the clock frequency of the SDRAM is hclk ): R_cnt = 2 ^ 11 + 1-SDRAM clock frequency (MHz) * SDRAM refresh cycle (US) When the PLL is not used, the SDRAM clock frequency is equal to the crystal oscillator frequency 12 MHz; the SDRAM refresh cycle is indicated in the Data Manual of the SDRAM, which is used in the data manual of the SDRAM HY57V561620CT-H of this development board, we can see this line "8192 refresh cycles/64ms": Therefore, the refresh cycle is 64 ms/8192 = 7.8125 us. In this experiment, r_cnt = 2 ^ 11 + 1-12*7.8125 = 1955, Refresh = 0x008e0000 + 1955 = 0x008e07a3   Banksize register: BanksizeIP address 0x48000028 Burst_en [7] ARM core burst operation allowed 0 -- prohibit unexpected operations 1-Allow burst operations Reserved [6] not used Scke_en [5] scke allow control 0 = SDRAM scke disabled 1 = SDRAM scke allowed Sclk_en [4] sclk is only allowed in the access cycle of the SDRAM During the Period of power consumption reduction. Sclk changes to 'L' during access 0 = sclk always activated 1 = SDRAM is only activated during access (recommended) Reserved [3] not used Bk76map [2: 0] bank6/7 storage ing 010 = 128 MB/128 MB 001 = 64 MB/64 MB 000 = 32 MB/32 MB 111 = 16 Mb/16 MB 110 = 8 Mb/8 Mb 101 = 4 MB/4 MB 100 = 2 MB/2 MB   Bit [7] = 1: Enable burst operation Bit [5] = 1: SDRAM power down mode enable Bit [4] = 1: sclk is active only during the access (recommended) Bit [2:1] = 010: bank6, bank7 corresponding address space and BANK0-5 is different. The BANK0-5 address space is fixed 128 m, the address range is (x * 128 M) to (x + 1) * m, X represents 0 to 5. However, the starting address of bank7 is variable. You can use "Table 5-1" in Chapter 5th of the S3C2410 Data Manual. in "Bank 6/7 addresses", we learned the relationship between the address ranges of bank6 and 7 and the address space. This development board only uses 64 MB space of bank6. We can make the bits [2: 1] = 010 (128 M/128 M) or 001 (64 m/64 m): It doesn't matter, the extra space program will detect and will not use non-existent memory. Both the introduced Bootloader and Linux kernel perform memory detection. Bit [6] and bit [3] are not used   SDRAM mode register settings register (mrsr ): Mrsrb6Address 0x4820.2c Mrsrb7IP address 0x48000030 Can let us modify only the bit [] (CL), SDRAM HY57V561620CT-H does not support Cl = 1, so the bit [] value is 010 (CL = 2) or 011 (CL = 3 ).