26. Core initialization close MMU and cache

26. Core initialization close MMU and cache

Look at the arm storage System below:

You can see that the fastest is the processor and the internal registers, their number is very small, the price is very expensive. followed by the TCM tightly coupled memory: cache and main memory. The slowest is the external storage media: Flash and SD card.

CACHE:

The above is two kinds of mechanisms to be accessed, one is the processor directly to the main memory, the other is the processor-cache-main memory. In the first case, the processor speed is very fast compared to main memory, so the speed of the two is very mismatched. Waste a lot of the processor's resources. The second is to improve the first defect, between the processor and main memory to add an original called cache, the cache access faster than main memory, slower than the processor, thus easing the first kind of resource waste phenomenon.

In fact, in the cache is stored in the main memory of some data copy: When the processor to access the main memory in the data, the processor will first go to the cache inside, if there is no data to be wanted, and then to the memory inside the access, at this time in addition to the data in memory to the processor, he also copied a data to the cache The next time the processor accesses the data, go to the cache to find it, if any, take it away directly. No access to main memory. Some people have done statistics, that is, the processor will use some data frequently, some data processors have been used for a long time. This greatly improves the speed of the visit.

The cache is a small but fast-access memory that holds copies of data from the most recently used memory. For programmers, the cache is transparent. It automatically determines what data is saved and what data is overwritten. According to the function division:

I-cache: Instruction Cache, for storing instructions

D-cache: Data Cache for storing data

2440 of I/d-cache:

6410:

210:

Virtual Memory:

If a programmer, write three programs, all need to access memory. And there are other applications in the operating system. As programmers, however, are surface-operated, and programmers simply know how to write software. How do they know which physical addresses are being used? What physical address does he use to not conflict? Finally, it is likely that two applications will access the same physical memory, resulting in an address conflict. There is also the actual physical address range is very limited.

However, after the virtual address has been introduced, programmer application programmers do not need to know which physical addresses are used because they are using virtual addresses. Even if three applications use the same virtual address, the system will then map the three virtual addresses to different physical addresses for execution. This will not create a conflict. This allows programmers to use a much larger range of virtual addresses than physical addresses.

Virtual Address: The address used by the program

Physical Address: Physical storage unit actual address

Virtual Address:

1. Allows the process to use a larger space
2. Can resolve conflicts

So who is going to implement virtual memory to physical memory conversion? This is the problem that the following MMU solves.

The mechanism of the MMU:

Above is the location of the MMU, complete the virtual address to the physical address conversion. Before the structure sees the cache in ARM11, the cache is between the MMU and the processor. After arm, the cache is between the MMU and main memory.

To use the MMU and the cache, these two must be learned to use, here to turn it off is I do not have to the MMU and the cache, because their use of two if not properly configured, there will be some unexpected errors. So let's turn them off first, lest there be any learning that will affect bare metal.

2440 I, Dcache invalid settings:

First enter the ARM920T nuclear handbook arm920t_trm1_s.pdf, search CP15:

Navigate to 2.3 CP15 Register Map Summary

I have a control register in CP15:

To navigate to the register, you can see its access method read and write:

MRC P15, 0, Rd, C1, C0, 0; Read Control register

MCR P15, 0, Rd, C1, C0, 0; Write Control Register

In this register, how to set off I, Dcache, and MMU, look at the parameters of the control register below:

As can be seen, the control I cache is [12] bit, the bit set to 0 is disable I cache,1 for enable. Control d cache is [2] bit, the bit set to 0 is to turn off D cache. The [0] bit is the control MMU, set to 0 is off, set to 1 is enable. So the job of shutting down I/D cache is to set the above three bits to 0.

But at first, the I/dcache already had data in it. So we also need to do data invalidation operations on it:

Command:

MCR p15,0,rd,c7,c7,0

As the above information knows, the operation to close the I/D cache and the MMU is:

1. Invalidates the I/D cache and MMU: MCR p15,0,rd,c7,c7,0
2. Then close the i/d cache and the MMU.

The first is to invalidate the I/D cache and the MMU, where the general register is selected R2:

MCR p15,0,r2,c7,c7,0

Close the MMU and cache:

MRC p15,0,r2,c1,c0,0 @ Read Control register

Bic R2,R2, #0x00000805 @0b100000000101=0x805

MCR p15,0,r2,c1,c0,0 @ Write control register

The final code:

Here is the 2440 setting, 6410 and 210 are the same operation. The CP15 of the three mentioned above are the same.

6410:

MRC P15, 0, <rd>, C1, C0, 0

MCR P15, 0, <rd>, C1, C0, 0

MCR cp15,0,r1,c7,c10,0

210:

26. Core initialization close MMU and cache