3.Makefile Engineering Management

3.Makefile Engineering Management

First, experience

As you can see in the previous notes, the compilation steps required to compile a simple project are many. There is still only one assembly file, in a project, there will be a lot of files, if like the previous way of compiling is very unreliable. This requires makefile Engineering management.

For example, the LED on the front. S, the steps to compile into Led.bin: Figure 1-1:

ARM-LINUX-GCC-G-C LEDs. S

Arm-linux-ld-tled.lds-o led.elf LED.O

Arm-linux-objcopy-o binary led.elf Led.bin

Figure 1-1

After the three steps above, the Led.bin is compiled. See inside there is also a makefile file, inside the content: Figure 1-2:

all:led.o

???? Arm-linux-ld-tled.lds-o led.elf LED.O

???? Arm-linux-objcopy-o binary led.elf Led.bin

????

Led.o:led. S

???? Arm-linux-gcc-g-O led.o-c led. S

????

. Phony:clean

Clean

???? RM *.o Led.elf Led.bin

Figure 1-2

Perform make in this directory, effect: Figure 1-3:

Figure 1-3

See, a make command and a bunch of commands above get the same result. So it is necessary to study makefile.

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Second, the use of makefile:

It is important to use the GNU make tool to manage engineering. A makefile project makes it easier to compile a project. Only one make command is required. The execution of make is primarily dependent on a makefile file. This file is a series of rules for compiling, linking, and so on. These rules include how to compile the source files in the project and how to produce the target files.

Third, the composition of makefile:

The composition of a makefile is actually very simple, that is, rules and variables . The so-called rule is how to produce a target file. The format of the rule: Figure 1-4:

Figure 1-4

It is particularly important to note that indentation is pressed by the tap key.

For example, the previous makefile:

all:led.o

???? Arm-linux-ld-tled.lds-o led.elf LED.O

???? Arm-linux-objcopy-o binary led.elf Led.bin

????

Led.o:led. S

???? Arm-linux-gcc-g-O led.o-c led. S

????

. Phony:clean

Clean

???? RM *.o Led.elf Led.bin

All is the ultimate goal, LED.O is the reliance on the final goal of production, the following command is the use of dependence, through the command to produce the final goal.

LED.O is also a goal, but not the ultimate goal, its dependence is Led.s, through the command to produce the target LED.O.

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There is also a pseudo-target concept in makefile. The so-called goal is only the command, no dependent target is called pseudo-target:

In the example above, use. Phony to declare a pseudo-target clean. The action performed by this pseudo-target is:

RM *.o Led.elf Led.bin

Final goal: If the user does not specify a rule to execute, make defaults to the first rule in Makefile, and the goal in this rule is called the final goal.

The following specifies the target of the makefile build, with the target not specifying the build: Figure 1-5:

Figure 1-5

As you can see, when make is followed by the specified target, he executes the target, and when there is no target to be generated, the default is the final goal. such as 1-5:

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Iv. variables in the makefile:

???????? Note that the variable in makefile is not of type.

The following is the introduction of variables into the above makefile: Figure 1-6:

obj=led.o

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All: $ (obj)

???? Arm-linux-ld–tled.lds–o led.elf $ (obj)

???? Arm-linux-objcopy–o binary led.elf Led.bin

????

Led.o:led. S

???? Arm-linux-gcc–g–o $ (obj) –c led. S

????

. Phony:clean

Clean

???? RM *.o Led.elf Led.bin

Figure 1-6

Compile to build the application smoothly. Figure 1-7:

Figure 1-7

Above is the definition and use of variables in the makefile file. There is no brevity, because the program is too simple.

In Makefile, in addition to the above user-defined variables, there are system default variables in makefile: Figure 1-8:

Figure 1-8

The following is a system customization of the three variables added to the above makefile file: Figure 1-9:

all:led.o

???? Arm-linux-ld-tled.lds-o led.elf $^

???? Arm-linux-objcopy-o binary led.elf Led.bin

????

Led.o:led. S

???? ARM-LINUX-GCC-G-o [email protected]-C $^

????

. Phony:clean

Clean

???? RM *.o Led.elf Led.bin

Figure 1-9

To work correctly:

This is part of simplifying makefile.

When there are multiple files of the same type in makefile, the same type of target file can be simplified by using the same command. First compile the project: Figure 1-10:

This is the makefile of the project:

all:led.o

???? Arm-linux-ld-tled.lds-o led.elf $^

???? Arm-linux-objcopy-o binary led.elf Led.bin

????

%.O:%. S

???? ARM-LINUX-GCC-G-o [email protected]-C $^

????

. Phony:clean

Clean

???? RM *.o Led.elf Led.bin

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Figure 1-10

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So when there are a lot of. When the S file is compiled into an. o file, using the simplified method above makes the Makefile project a lot more brief.

Above is the basic usage of makefile.

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V. Remove Echo:

In the above operation, it is found that when the make command is executed, the compilation process is called Echo, and when the project is very large, this time is very time-consuming. So it is necessary to go back to the show. To go back to show is actually very simple is to add the @ symbol before the command: Figure 1-11:

Not added @ before:

After joining @:

Figure 1-11

As seen from the above running results, after adding @ before the command, the compilation generates Led.bin without echoing back.

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Six, makefile Parameters:

Finally, it is important to note that in the Makefile project, it is not necessary to name the project file makefile, which is for convenience and can be named according to need. Only the command to compile the project is different. For example the name of the project file is forfish. The process of compiling, such as 1-12:

The command is:make–f forfish: is the make command + parameter-f+ project file:

Figure 1-12

You can see that the result of the compiled project is the same as the previous effect.

3.Makefile Engineering Management