(4) DRAM Sizing

[Q] Why is stable memory so important?
A: Because there are too many things to store on it, for example, BIOS code (which will be mentioned in the shadow section later), device drivers and OS, Etc... if the memory is unstable, you cannot obtain the required data when accessing memory, or you cannot even read or write data, you will find that the system hang (maybe randomly) during post is not used, or blue screen...

Therefore, "Poor bios dram Sizing" is one of the reasons for system instability (the Foundation is unstable, how can we expect the house to be sturdy)

Before introducing DRAM sizing, we should briefly describe dram-related knowledge.
(If there are any deficiencies or errors, please ignore them ...)

1. dram chip can be seen as square array; the basic unit is cell. each cell is composed of several transistors (depends on cell width; remember: 1 bit is composed of one transistor, which records the information of 0 and 1; 1 cell may contain N bits; reading DRAM cells is destructive, so reading is often accompanied by "refresh" <-different from SRAM)

2. to access data in dram chip, the row and column address must be provided; the two addresses are sequential; meaning: Row address is sent first, and then column address to chip.
(Echo the above: Square Array, similar to the X, Y addressing) the final data will be put on the data bus, and the CPU will read

* If you have time, check the Internet: Why is the pins required by dram chip halved (half)? ^_^

3. DRAM controller is usually used in chipset, Ex. NB (AMD K8 CPU is the memory controller in the CPU, for better performance); its job is interfacing dram chip; other devices (ex. CPU, DMA controller... etc) the bridge between dram chip!

Ex. In bios, write the following code to "read", "Memory", "Location 8" data:
XOR ax, ax
MoV es, ax
MoV EDI, 00000008 H
MoV Al, byte ptr es: [EDI]

[00000008 H] is the linear address known by programmer, but dram chip only recognizes MA0 ~ Max, ba0 ~ Ba1.. etc signal, how to communicate? => Switch by DRAM controller !!!

4. DRAM access time => the time from dram chip to address signals until valid data appears on the Data Bus (assume "read" memory), which is also one of the features of dram chip.

5. the common DRAM is DDR/DDR2 SDRAM. the so-called "S" Dram refers to synchronous DRAM, that is, DRAM operation is performed by referring to a clock, that is, synchronous ). DDR refers to double data rate, that is, data can be transmitted in the rising and falling edge of clock. DDR2 refers to the "second generation" of DDR "! (Do not think of it as DDR2 = DDR x 2 !!! Although some values have a double relationship ...)

Ex. DDR2 533 (or called PC2 4200) =>
1. "2" means DDR2
2. 533 is transfer rate (533 pieces of information can be written per second)
3. 4200 means: 533 pieces of data/S * Each 8 bytes (=> 64 bit width )~ = 4200 MB/S

DRAM SizingProgramIt is closely related to chipset design. Different chipsets have different DRAM sizing sequence. Only rough sequence is listed here for reference. (the actual detailed sequence must be subject to the Code of each family)

[Hypothesis]:
A. Memory Controller Integrated into Nb
=> Some part of Nb PCI config space is related to dram.
B. This chipset support 4 DRAM sockets (max .)
=> 4 registers exist, representing the 4-socket drams 'information
=> 4 BITs exist, respectively controlling 4-socket's CS (chip select; Enable DRAM used)

[Program]
1. Configure registers by DRAM frequency:
=> Registers (ex. trfc, TRP, trcd, twtr, Cas ,... etc) must be set according to DRAM operating frequency. (DRAM frequency can be obtained from CPU freq and CPU/DRAM ratio)

2. Execute Initial Sequence for DDR (or DDR2)
=> DRAM spec has an initial sequence column.

3. Set max-supported size of this chipset for 4 sockets!
=> Because "I don't know" how big the dram is, assume that each socket has DRAM inserted, and the size is-> the maximum size supported by this chipset (ex. 2G)

4. Do the followings for socket 0/1/2/3 sequentially (<-"Only enable 1 socket" at a time)

1) Check DRAM exist or not
=> Simply write-then-read pattern is used to determine whether the socket has installed dram.

2) Decide DRAM "type" If DRAM exist
=> If DRAM is on a socket, obtain its "type" information.
Taking DDR2 SDRAM as an example, this step is to obtain information about the memory (bank, row, column, side ).
Ex. 2x12x9's Dram and double side, the memory size is 128 MB

* Find DRAM information with Ma table & by SPD.

3) write this information to corresponding register

5. Configure registers by DRAM Loading
=> After Step 4 is completed, all installed DRAM has been found. in this case, you need to adjust some DRAM registers related to "loading" (because different DRAM numbers must have different driving strength !)

6. Remaining tasks:
=> Disable one-page Mode
Enable dynamic Reset
Enable refresh cycle (<-DRAM is OK to use limit _^)

[Note]
1. Now the top memory ("maximum memory available" already... determines the memory _^)
2. There is no rigorous tests on dram in this stage.
3. Generally, if register config is incorrect or DRAM frequency is incorrect (due to clockgen config error), Hang will be in this stage! If the system is lucky to pass this stage to DOS, you can use memory test utility to verify DRAM is stable or not !!!

[Supplement]
Before this stage (sizing) is complete, DRAM is not ready to use. Therefore, when writing this code, the cpu gpr (general purpose register) must be used to pass the parameter or return address! Therefore, always pay attention to whether the register content is changed (because GPRS is not much ...)

However, if activate car (Cache as Ram) is used, push/pop can be used in this stage, and the code written will be more modular and elastic, you don't have to worry that register content will be damaged...
Ex. AMD kx sizing Code uses cache as Ram very early, so we can write module code for sizing !!!

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