44b0 boot comments

**************************************** ***************
; * Name: 44binit. S *
; * Version: 10. jan.2003 *
; * Description :*
; * C start up codes *
; * Configure memory, initialize ISR, stacks *
; * Initialize C-variables *
; * Fill zeros into zero-initialized C-variables *
; **************************************** ***************

Get option. s; equivalent to # I nclude "option. s" in C"
Get memcfg. s

; Interrupt control
Declare some symbolic constants that correspond to the addresses of the corresponding registers
Intpnd equ 0x01e00004; indicates that each bit in the interrupt request status register changes to one type of interrupt request. For details, refer to 44b0 spec.
Intmod equ 0x01e00008; the interrupt mode register has two kinds of interrupt mode. The corresponding bits are 1, indicating that FIP Mode 0 represents Riq mode.
Intmsk equ 0x01e0000c; Determine which interrupt source is blocked and the blocked interrupt source will not be served
I _ispr equ 0x01e00020; interrupt service suspension register
I _cmst equ 0x01e0001c; current Master Register IRQ priority

; Watchdog timer
Wtcon equ 0x01d30000; watchdog timer control register

; Clock Controller
Pllcon equ 0x01d80000; PLL control register
Clkcon equ 0x01d80004; clock control register
Locktime equ 0x01d8000c; lock time count value register

; Memory Controller
Refresh equ 0x01c80024; DRAM/SDRAM refresh control register
The following is a constant definition of the value corresponding to the ARM processor mode register. The ARM processor has a CPSR Program Status Register. Its last five digits determine the current processor mode.
; Pre-defined Constants
Usermode equ 0x10; 0b10000 user mode
Fiqmode equ 0x11; 0b10001fiq Mode
Irqmode equ 0x12; 0b10010irq Mode
Svcmode equ 0x13; 0b10011 Management Mode
Abortmode equ 0x17; 0b10111 Stop Mode
Undefmode equ 0x1b; 0b11011 undefined
Modemask equ 0x1f; 0b11111 System Mode
Noint equ 0xc0;

; Check if tasm.exe is used.
The ARM processor has two working states: 1.arm: 32-bit. In this working state, the arm command executes the word aligning. 2. Thumb: 16-bit. In this working state, the half-word aligning thumb command is executed.
Because the processor is divided into 16-bit 32-bit working state, the compiler of the program is also divided into 16-bit and 32-bit compilation methods, so the following program is used to determine the compiler compilation mode based on the working state of the processor.
Code16 pseudo commands indicate 16-bit thumb commands after the compilation Compiler
Code32 pseudoinstruction indicates the 32-bit arm instruction after the Assembly Compiler
This section describes the operating status of the processor and the software compilation formula (16-bit compiling environment is translated using tasm.exe)
Gbll thumbcode; set a global variable
[{Config} = 16; If Config = 16 this indicates that you are currently in the leading 16-bit compiling mode.
Thumbcode SETl {true}; Set thumbcode to true
Code32; transfer to 32-bit compiling Mode
| Times; else
Thumbcode SETl {false}; Set thumbcode to false
]

[Thumbcode; If thumbcode = true
Code32; for start-up code for thumb mode; transfer to 32-bit compilation Mode
]
Note: The following program is a macro definition. Many people do not understand this program. I emphasize that this is a macro definition. Therefore, you must note that the following handlerxxx handler handlexxx will be expanded in the following program.
This program is used to load the first address of the interrupted service program to the PC. Someone calls it "loading the program ".
The initialization program defines a data zone (at the end of the file) with 34 characters to store the first address of the corresponding interrupted service program. Each word space has a label named after handle.
In vector interrupt mode, use "loader" to execute the interrupt service program.
Here we must talk about the concepts of the vector interrupt mode and the non-vector interrupt mode.
In vector interrupt mode, when the CPU reads the IRQ interrupt command at 0x18, the system automatically reads the command at the specified address of the interrupt source to replace the command at 0x18, jump directly to the corresponding address through the jump command system
The function saves the interrupt processing time and increases the interrupt processing speed. For example, if the vector address of the ADC interrupt is 0xc0, run the following code at 0xc0: ldr pc, = handleradc the system will
; Automatically jump to the handleradc Function
Non-vector interrupt mode is a traditional interrupt processing method, the system redirects the corresponding flag position in the interrupt pending register to the unified interrupt at 0x18.
In the function, the function reads the corresponding flag in the interrupt pending register to determine the interrupt source and jumps to the processing code of the corresponding interrupt source based on the priority relationship.
Macro
$ Handlerlabel handler $ handlelabel

$ Handlerlabel
Sub sp, SP, #4; Decrement Sp (to store jump address)
Stmfd SP !, {R0}; push the work register to stack
; R0 register to be used into the stack
LDR r0, = $ handlelabel; load the address of handlexxx to R0
LDR r0, [R0];
STR r0, [Sp, #4]; store the contents (ISR) of handlexxx to stack
; Add the first address of the interrupt function to the stack.
Ldmfd SP !, {R0, PC}; pop the work register and PC (jump to ISR)
; Put the first address of the interrupt function out of the stack into the program pointer. The system will jump to the corresponding interrupt processing function.
Mend
An arm consists of three segments: RO, RW, and Zi. Ro is the code segment, and RW is the initialized global variable, zi is an uninitialized global variable (the GNU tool corresponds to the concept of text, Data, BSS) bootloader
; Bootloader needs to copy the RW segment to Ram and clear the Zi segment. The compiler uses the following segment to record the start and end addresses of each segment.
; | Image $ Ro $ base |; start address of the RO segment
; | Image $ Ro $ limit |; Add 1 to the end address of the RO segment
; | Image $ RW $ base |; start address of the RW segment
; | Image $ RW $ limit |; Add 1 to the RW segment end address
; | Image $ Zi $ base |; start address of the Zi segment
; | Image $ Zi $ limit |; Add 1 to the end address of the Zi segment
The value of these labels is determined by the compiler settings, such as the ro-base and RW-base settings in the compilation software, such as ro-base = 0xc000000 RW-base = 0xc5f0000

Import | image $ Ro $ limit |; end of ROM code (= start of Rom data)
Import | image $ RW $ base |; base of Ram to initialise
Import | image $ Zi $ base |; base and limit of area
Import | image $ Zi $ limit |; to zero initialise

Import main; the main entry of Mon Program
; Below is the code snippet
Area init, code, readonly

; Abnormal interrupt vector table (each table entry occupies 4 bytes) the following figure shows the interrupt vector table. Once the system is running, the interrupt occurs. Even if the operating system is transplanted, for example, the Linux processor has handed over the control to the operating system, the processor will jump from 0x0.
An interrupt table entry in the interrupt vector table (based on the interrupt type ).
For details about the interrupt vector layout, refer to the 49th position vector address 0x0 + 4 * (49-1) = 0x000000c0 In the table corresponding to the position vector in the spec. For example, the ADC interrupt vector is 0x000000c0.
Entry
After the wrench is powered on and reset, the program starts to execute from 0x0. After the hardware is powered on and reset, the program starts to execute from here and jumps to the resethandler to execute.
B resethandler; For debug
B handlerundef; handlerundef
B handlerswi; SWI interrupt handler
B handlerpabort; handlerpabort
B handlerdabort; handlerdabort
B.; handlerreserved
B handlerirq
B handlerfiq
; *** Important note ***
; If the H/W vectored interrutp mode is enabled, the above two instructions shoshould
; Be changed like below, to work-around with H/W bug of fig.
; B handlerirq-> subs PC, LR, #4
; B handlerirq-> subs PC, LR, #4

Vector_branch
Ldr pc, = handlereint0; mga h/W interrupt vector table
Ldr pc, = handlereint1;
Ldr pc, = handlereint2;
Ldr pc, = handlereint3;
Ldr pc, = handlereint4567;
Ldr pc, = handlertick; MGA
B.
B.
Ldr pc, = handlerzdma0; MGB
Ldr pc, = handlerzdma1;
Ldr pc, = handlerbdma0;
Ldr pc, = handlerbdma1;
Ldr pc, = handlerwdt;
Ldr pc, = handleruerr01; MGB
B.
B.
Ldr pc, = handlertimer0; MGC
Ldr pc, = handlertimer1;
Ldr pc, = handlertimer2;
Ldr pc, = handlertimer3;
Ldr pc, = handlertimer4;
Ldr pc, = handlertimer5; MGC
B.
B.
Ldr pc, = handlerurxd0; MGD
Ldr pc, = handlerurxd1;
Ldr pc, = handleriic;
Ldr pc, = handlersio;
Ldr pc, = handlerutxd0;
Ldr pc, = handlerutxd1; MGD
B.
B.
Ldr pc, = handlerrtc; mgka
B .;
B .;
B .;
B .;
B. mgka
B.
B.
Ldr pc, = handleradc; mgkb
B .;
B .;
B .;
B .;
B.; mgkb
B.
B.
; 0xe0 = enterpwdn
Ldr pc, = enterpwdn

Ltorg
The following is the macro to jump to the specific interrupt handler function. The macro definition of $ handlerlabel above is expanded to jump to the corresponding interrupt handler function (for vector interrupt)
Handlerfiq handler handlefiq
Handlerirq handler handleirq
Handlerundef handler handleundef
Handlerswi handler handleswi
Handlerdabort handler handledabort
Handlerpabort handler handpolicabort

Handleradc handler handleadc
Handlerrtc handler handlertc
Handlerutxd1 handler handleutxd1
Handlerutxd0 handler handleutxd0
Handlersio handler handlesio
Handleriic handler handleiic
Handlerurxd1 handler handleurxd1
Handlerurxd0 handler handleurxd0
Handlertimer5 handler handletimer5
Handlertimer4 handler handletimer4
Handlertimer3 handler handletimer3
Handlertimer2 handler handletimer2
Handlertimer1 handler handletimer1
Handlertimer0 handler handletimer0
Handleruerr01 handler handil-err01
Handlerwdt handler handlewdt
Handlerbdma1 handler handlebdma1
Handlerbdma0 handler handlebdma0
Handlerzdma1 handler handlezdma1
Handlerzdma0 handler handlezdma0
Handlertick handler handletick
Handlereint4567 handler handleeint4567
Handlereint3 handler handleeint3
Handlereint2 handler handleeint2
Handlereint1 handler handleeint1
Handlereint0 handler handleeint0

; One of the following two routines can be used for non-Vectored Interrupt.
The following program is used to handle non-vector interruptions. In I _ispr, if you set 1 to 1, this interrupt is waiting for response (only one position is allowed at a time ), starts from the highest priority interrupt bit and detects waiting for the service.
When the service is interrupted, the PC is set to the first address of the function to be interrupted.
Isrirq; using I _ispr register.
Sub sp, SP, #4; reserved for PC
Stmfd SP !, {R8-r9}

; Important caution
; If I _ispc isn' t used properly, I _ispr can be 0 in this routine.

LDR R9, = I _ispr
LDR R9, [R9]
MoV R8, #0x0
0
Movs R9, R9, LSR #1
BCS % F1
Add R8, R8, #4
B % B0

1
LDR R9, = handleadc
Add R9, R9, R8
LDR R9, [R9]
STR R9, [Sp, #8]
Ldmfd SP !, R8-r9, PC}

; **************************************** ************
; * Start *
; **************************************** ************
After the wrench is powered on and reset, the program starts to execute the B resethandler program from 0x0 and starts to jump to here for execution.
After the Board is powered on and reset, perform several steps. Here, add 1, 2, 3... to the comment to indicate the sequence of execution.
1. Disable the watchdog to block all interruptions.
Resethandler
LDR r0, = wtcon; watch dog disable
LDR R1, = 0x0
STR R1, [R0]

LDR r0, = intmsk
LDR R1, = 0x07ffffff; all interrupt disable
STR R1, [R0]
2. Set the PLL according to the working frequency
Here we will introduce the calculation formula
; Fpllo = (M * fin)/(p * 2 ^ s)
; M = mdiv + 8, P = pdiv + 2, s = sdiv
; Fpllo must be greater than 20 MHz and smaller than 66 MHz
; Fpllo * 2 ^ s must be less than 170 MHz
; M_div p_div s_div in pllcon settings below is taken from option. h
; # Elif (mclk = 40000000)
; # Define pll_m (0x48)
; # Define pll_p (0x3)
; # Define pll_s (0x2)
So M = mdiv + 8 = 80, P = pdiv + 2 = 5, S = sdiv = 2
The hardware uses a 10 MHz crystal oscillator, that is, fin = 10 MHz.
; Fpllo = 80*10/5*2 ^ 2 = 40 MHz

; **************************************** ************
; * Set clock control registers *
; **************************************** ************
LDR r0, = locktime
LDR R1, = 800; Count = t_lock * fin (t_lock = 200us, fin = 4 MHz) = 800
STR R1, [R0]

[Pllonstart
LDR r0, = pllcon; temporary setting of PLL
LDR R1, = (m_div <12) + (p_div <4) + s_div); fin = 10 MHz, fout = 40 MHz
STR R1, [R0]
]

LDR r0, = clkcon
LDR R1, = 0x7ff8; All unit block CLK enable
STR R1, [R0]
3. Set the program for storing the relevant registers
This is the Program for configuring the connection and Working Sequence of the SDRAM, Flash ROM memory, and the program defined by the chip selection.
; Smrdata map is defined in the following program
For the values involved in smrdata, see the memcfg. s program.
For more information about the registers, see

; **************************************** ************
; * Set memory control registers *
; **************************************** ************
LDR r0, = smrdata
Ldmia r0, {R1-R13}
LDR r0, = 0x01c80000; bwscon address
Stmia r0, {R1-R13}

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