64-bit open source processor rocket's source code simple introduction

Recently, I probably read the source code of the rocket processor released by UCB, and have some general knowledge about the functions of each file in the source, mark.

Rocket is a 64bit scalar processors, 5-stage pipeline, using the risc-v instruction set, integrated FPU, and has many or1200 features, such as: Non-blocking cache, branch prediction, return address stack, hardware page table fill, cache support ECC, support multicore and so on.

The source code for rocket is written using chisel, Chisel is a Scala-based domain-specific language for UCB release. Can download rocket all the source code in Https://github.com/ucb-bar/rocket, a total of 20 files, the functions of each file implementation are as follows:

Open Source Processor rocket source code file role Description

Arbiter.scala	A fixed-priority arbiter is implemented, with lower numbers and higher precedence
Btb.scala	Implements the Gshare, which contains BTB (Branch Target Buffer), BHT (Branch history Table), and also implements the RAS (Return Address Stack)
Consts.scala	Defines a number of faces that are similar to macro definitions
Core.scala	Includes control pathways, data paths, and unites as core
Csr.scala	The control Status registers defined in the RISC-V instruction set is implemented.
Ctrl.scala	Realization of the control path, which reflects the 5-stage pipeline
Decode.scala	It realizes the simplification of the Karnaugh map, and uses the function here when the instruction is decoded.
Dpath.scala	Implementing a Data path
Depath_alu.scala	Implements the Alu
Fpu.scala	Interface to the third-party FPU is implemented
Icache.scala	Implementation of instruction-level caching, value, which uses the branch prediction technology defined in Btb.scala
Instructions.scala	Defines all the instructions supported by the rocket processor
Multiplier.scala	Multiplication and division are implemented, in which multiplication uses iterative methods, and division uses the trial commercial law
Nbdcache.scala	Implementation of data-level caching with MSHR technology for nonblocking caching
Package.scala	Defines a reset address, exception handling vector base Address
Ptw.scala	Implements the Hardware page table walk, which is the hardware sheet fill
Rocc.scala	Implements an accelerated coprocessor to execute user-defined directives
Tile.scala	The top-level file of the rocket processor, which connects core, instruction-level cache, data-level cache, FPU, and other modules
Tlb.scala	Implements the transmit backup buffer
Util.scala	Some objects are defined, and some tool functions are provided, such as: type conversion.

The above is a personal understanding, welcome everyone to raise objections, joint discussion ah.

64-bit open source processor rocket's source code simple introduction