6.5 Control signal of the branch instruction

The computer consists of a control signal of 6 single cycle processor 6.5 branch Instruction

A branch instruction is a special kind of instruction that can change the flow of a program. Therefore, to implement the branch instructions, we also need to further transform the existing structure.

In our present example of the instruction system, the branch instruction has only one, its format is type I, then we first look at how the branch instruction works.

On the left is a C language code, is a typical if Else statement, then we see how to generate MIPS of the assembly language code will be how. The first is a beq branch instruction, it appears that the compiler has put I and j these two local variables in the S3 and S4 the two registers, then this instruction is to compare S3 and S4 values. If they are equal, they will jump to True the address indicated by the label, which is an addition instruction that executes the F=G+H statement. That is, the C language code, if the condition is true, the statement to be executed. After executing this statement, the program executes the subsequent contents in sequence.

If the judgment condition of the IF statement is not established, then the corresponding BEQ instruction will be executed, and the contents of the S3 and S4 registers are not equal, so that the branch transfer does not occur, but the following instruction of the order is executed. The latter instruction is a subtraction instruction, which corresponds to the addition instruction we saw just now, in fact, it executes the F=G-H statement. That is the phrase in C, else. Then after executing this instruction, the next instruction is an unconditional transfer instruction that jumps directly to next, which is an example of applying conditional branching instructions. So let's take a look at how the control signal for the BEQ command is generated.

The operation of the beq instruction can also be divided into three steps. The first is to take the instruction; the second one is to determine whether the contents of the RS and RT two registers are equal, so we can judge by a subtraction; the third step is to update the PC registers.

So for the BEQ directive, the so-called branch is how to rewrite the PC register. So its focus is on the third step.

We first look at the condition is not established, that is, else corresponding to the pc=pc+4, that when the transfer conditions are not established, we are sequentially executed after an instruction (that is, the sub command in the previous PPT),
This is the same as the other arithmetic instructions, the FETCH command.

If the condition is set up, the update condition of the PC is relatively complicated. There are also pc+4, which need to be added with this 16-bit immediate number symbol extension and multiplied by 4. That is, in the BEQ directive, the immediate number that is taken, that is, the label of the target address that was just shown in the example is true, and its actual value is the difference between the transfer destination address and the next instruction address (the address at true addresses minus the address at the Sub command), and this difference is 4 bytes, That is, 32 bits for one unit. Then this rule is agreed upon when formulating the MIPS instruction system. Our focus now is on how to achieve the corresponding control signals.

Again, we look directly at the second step. So for this step, the actions to be taken include removing the contents of two registers from the register heap, and doing the subtraction operation, which is the same as the requirements of the subtraction command we learned earlier. As a result, the existing structure does not need to be modified to complete this function. We note that when retrieving an instruction, the RS bit field is connected to the register heap, the contents of the register it designates are placed on the BUSA and connected to an input of the ALU, and the signal of the RT bit field is connected to the input of the RB of the Register heap, and the contents of the register specified by the BUSB signal, Pass this (ALUSRC) multi-selector to another input of the ALU, then this ALU can perform this subtraction. The problem, however, is that the previous subtraction instruction will write the result of the ALU operation back to the Register heap (RegFile) through the multi (memtoreg) selector. The beq instruction is not required to write back to the register heap, and should not be written back. We hope that through this alu, we can draw a judgment that the result of this subtraction operation is not 0. Therefore, we also need to add a new function to complete such a judgment: to determine whether a number equals 0. This is very simple, so we can easily add this function in the ALU, and let the ALU provide a signal output, indicating whether the current operation is 0, we named the Signal zero. If the result of the operation is 0,alu, the zero signal is set to 1; otherwise, it is set to 0. That is because the result of the operation is 0, it will affect how Ifu to update the PC register, so we need to connect the zero signal to the IFU. In this way, we can add a complete description of the second operation.

So in this step operation, how is the red control signal set?

First of all, the next PC selection method, we can no longer set to add 4. But how exactly to update, Ifu still need to do some work, this we say later. So we'll first mark the selection signal as branch, and then we'll look at the other control signals.

Now we know that the ALU is going to perform a subtraction operation, and that its two operands should come from the register heap, so this selector should choose Channel 0 (alusrc=0). As a result, the extended part function selection signal can be set arbitrarily (extop=x). The function of the ALU to select the signal, you need to set to subtract (aluctr= "SUB"), and now although we have added this zero signal, but the original function of the ALU still must be maintained. So, when we set the ALU to perform the subtraction operation, its output is still the result of the subtraction operation, and it is sent to the address side (ADR) of the data memory and the channel No. 0 of the next selector. To ensure that the data memory is not rewritten, we also set the write enable signal for the data memory to be 0 (memwr=0). For conditional branch instructions, it is not to write back to the register heap, so this multi-selector regardless of which channel to choose, it is meaningless, then we can set its choice signal arbitrarily 0 or 1 (memtoreg=x).

Finally we look at this side of the Register heap (regfile), because there is no need to write back the register heap, so we have to set the register heap write enable signal is 0 (regwr=0), so as not to mistakenly change the contents of it, because the write enable signal has been set to 0, that register heap write register number, You can set any of the settings (regdst=x).

In this way, we can see that the BEQ command executes when the signal is really valid. However, we have to note that this step is only to complete the judgment, then we have to rely on the results of the decision to update the PC register. Therefore, the third step of this instruction is not the same as the other instructions.

Well, now for Ifu, it has two input signals, one is the previous NPC_ Select, and the other is the zero we added later.

And we know that the key to how the Ifu updates the PC registers is the question of how this selector is selected. Its channel No. 0 is connected to the pc+4,1 channel, which is the destination address of the branch instruction. So what should we do with this choice signal now? We might as well take a table of input columns to observe.

When the signal of Npc_select is 0, it means that the command being executed is an operation instruction, or a memory command, rather than a branch instruction. At this point, whether the zero signal is 0 or 1, the selector should select channel No. 0, which sequentially executes the next instruction.

When the npc_select signal equals 1 o'clock, a branch instruction is currently executing. However, if the zero signal at this time is 0, indicating that the decision condition of the branch is not established, then the multi-selector should still choose channel No. 0, so that the next instruction in order to execute.

Only if the signal of the Npc_select is 1, indicating that the current is a branch instruction, and the zero signal is also 1, indicating that the current judgment condition is established. At this point, the selector can select channel 1th, so that the target address of the branch is updated to the PC register, so that in the next clock cycle, the instruction memory will be the branch destination address point to the code of the instruction to send out, so as to achieve the direction of instruction execution flow change.

And through this table, can we get a method for generating the control signal of this multi-selector? Please think about it. To give a hint, you actually just need a logic gate. If you haven't figured it out yet, we might as well come back and observe that for this selector signal, it will only be 1 if the npc_select and zero signals are 1 o'clock, and at other times, the selection signal is 0. So is this description familiar to everyone? What is the function description of the logic gate? Let's take a look at the far right, in fact, just need one with the door to be able.

Based on this analysis, we can further transform the IFU to support the requirements of the BEQ directive. But here's one more question, that is, how is the branch target address generated? So now we're going to do this last work, the branch destination address has two parts, part is Pc+4, part is the symbol expansion of the immediate number, and then multiplied by 4, and the immediate number is the low 16 bits in the instruction encoding, so we first connect this part of the signal.

Now, we take this immediate number out and connect it to a symbol extension part. For the part of this symbol extension, we add a very simple small function, that is, to move two bits to the left and two bits to the left is the equivalent of multiplying by 4. So, after this part, we've expanded the 16-bit immediate number to 32 bits, and we've done the operation multiplied by 4. Now we have the second half of the equation, and the first part is pc+4. Fortunately, we now have the pc+4, which is the output of this adder, so we just need to connect it directly, and then add a adder, so we can get the target address of the branch instruction.

Now this ifu, we have already added complete.

Now, we have analyzed the last instruction in this command system. We already know what value we should give each command, each control signal. But there is another problem, and we are still not very clear about how the values of these signals are automatically generated. We'll come together to discuss the issue in the next section.

6.5 Control signal of the branch instruction