6.SysTick System Clock Tick experiment (STM32 interrupt entry)

System Clock tick experiment is not difficult, I was in the face of the simple said, but it involves the most complex STM32 is the most widely used peripheral-nvic, if the RCC is the real-time needs to consider the part, then NVIC is stm32 functional realization of the foundation, NVIC difficulty is not high, But the understanding is still more complicated, I will in this article from the actual application to explain, of course, the best to study Song Yan translation of <cortex-m3 authoritative guide > Eighth, note this is not a book to teach you how to write STM32 code, It's a reference book that explains the cortex-m3 kernel principle, which is worth reading.

The core of the Systick system clock has two, peripheral initialization and systick_handle () interrupt handling functions.

Systick configuration:

Static void Systick_userconfig (void) {  SysTick0xfffffffb;  // using the external clock of the kernel, i.e. Systick  0x8000;       //   0x00;          // Systick Current Value Register clear 0  0x03;         // Systick timer Enable, interrupt enable }

Nvic configuration:

void Nvic_userconfig (void) {    nvic_setvectortable (nvic_vecttab_flash,0x0);      // point the pointer to the interrupt vector table in Flash }

Interrupt function:

 void   static  uint32_t Led_flag    = 0  ;  if  (Led_flag < 50  ) {led_1_on ();  if  (led_flag >= 50  ) {Led_1_off ();    } led_flag  ++;  if  (Led_flag = = 100   = 0  ; }}

This completes the simple SysTick tick experiment, the Code please refer to: http://files.cnblogs.com/files/zc110747/6.SysTick.7z

See this is not the end, but remember when I finished this program, questions have the following points:

1. How a vector table is defined, what is the role of the relocated operation

2. Why interrupt function name must be void Systick_handler (void), how to determine the

3. interrupts disrupt the normal program flow, how the CPU knows where to go back to the previous run

4. How interrupt prioritization is configured and understood

How to solve these problems, which need to be solved from the principle, understand the IAP and uc/os-ii of these issues should have a certain understanding, the following I will systematically explain my thoughts:

problem. The corresponding exception service routine (ESR) executes when the CM3 kernel responds to an exception that occurs. In order to determine the entry address of the ESR, this is known as the "vector table check table mechanism". A vector table is actually an array of WORD (32-bit integers), each subscript corresponding to an exception, and the value of the subscript element is the entry address of the ESR. If you look at STARTUP_STM32F10X_CL.S carefully, you will find the following statement:

; Vector Table Mapped to Address0At reset area Reset, DATA, READONLY export __vectors export __vecto Rs_end EXPORT __vectors_size__vectors DCD __initial_sp; Top of Stack DCD Reset_handler; Reset Handler DCD Nmi_handler; NMI Handler DCD Hardfault_handler; Hard Fault Handler DCD Memmanage_handler; MPU Fault Handler DCD Busfault_handler; Bus Fault Handler DCD Usagefault_handler; Usage Fault Handler DCD0                          ; Reserved DCD0                          ; Reserved DCD0                          ; Reserved DCD0                          ; Reserved DCD Svc_handler; Svcall Handler DCD Debugmon_handler; Debug Monitor Handler DCD0                          ; Reserved DCD Pendsv_handler; PENDSV Handler DCD Systick_handler; SysTick Handler; External interrupts DCD Wwdg_irqhandler; Window Watchdog ...DCD Otg_fs_irqhandler; USB OTG fs__vectors_end__vectors_size EQU __vectors_end-__vectors Area|. Text|, CODE, READONLY

Where _vectors is both the mentioned Word array, which is the defined vector table , if you know pointers to functions , then you can know that each of DCD is defined as the interrupt service routine, So we know why the interrupt service routine for the Systick interrupt is Systick_handler, and of course the vector table can implement an interrupted query as long as it is consistent with the main function code, such as modifying Pendsv_handler in a uc/os-ii migration.

See this solves the second problem, so the first question, as can be seen from the above, the vector table has been at the top of the code, that is, the offset of the location of 0x0, why sometimes need to reposition it? If you have seen the IAP, understand the startup mechanism, you should understand that the system will default to go to 0x00000000 (Flash address 0x08000000 map), and then read the vector table offset register, query vector table, because this time the vector table offset is 0x0, The vector table does not need to be redefined. In the IAP mode, the application code start address is not the flash address, but by the offset 0x8000 (assuming the value), from the above can also be simple to launch the application code of the vector table offset is also 0x8000, when the vector table offset register needs to be redefined.

The. map file generated from the list

Then refer to the generated bin file and startup file:

The above view can be clearly confirmed.

3. Understanding the M3 chip base should know that M3 has a universal Register Group R0~R15, which holds all the information about the code flow in the program run, including the current address, variable parameters that are being modified. So when the interrupt is triggered, as long as the r0~r15 in sequence, after the end of the stack, the code will go back to the position before the run (Uc/os-ii is to simulate the process to achieve task switching), of course, this is only the simplest case, because the M3 chip itself supports interrupt priority and interrupt nesting, The actual complexity is much higher than this. In fact, it can be simplified to the following process:

　　The main program pauses-〉 related position and state parameter into the stack-〉 interrupt Service routine executes-〉 related position and state parameter out of stack-〉 main program recovery

4. CORTEX-M3 supports up to 240 configurable interrupts, the number of interrupt priority 3~8 bits, which is 8~256 priority, and in fact does not support that much, such as the 8,16,32 level, where up to 128 preemption levels are supported. ARM interrupt and reset control registers the 3~8 bit set priority section, by configuration can be divided into two parts, preceded by preemption level, followed by sub-priority, and sub-priority is at least 1 bits, grouping can start from the reserved priority group. The priority of an interrupt can be judged in the following order, with the priority decreasing.

Priority groups: preemption > Sub-priorities

Priority: Small value > Large value

Interrupt Number: Small interrupt number > large interrupt number

The difference between preemption and sub-priorities:

Preemption is the basis on which interrupt nesting occurs, and the process of interrupting a thread is mentioned above, but if there is a preemption level join, the interrupt itself is interrupted by a higher priority interrupt, as follows:

　　Main program pause-〉 Low priority interrupt-〉 high priority interrupt-〉 low priority interrupt-〉 Main program recovery

A sub-priority indicates that there is no nesting of interrupts, and that an interrupt is only responded to by another sub-priority interrupt after it has ended, that is, no interrupt nesting occurs.

In addition, to speed up the process of interrupting execution, CORTEX-M3 provides four priority-based actions:

1. preemptive: occurs mainly in the preemption level, that is, high-priority interrupt low priority execution, interrupt nesting

2. at the end of the chain: If the preemption occurred at the end of the last interrupt before the stack, then interrupt the stack action, directly perform a high-priority interrupt, after the end if no preemption occurs, the execution of the stack

3. belated If the preemption occurs at the beginning of the interrupt into the stack phase, then continue into the stack, the low-priority interrupt hangs.

4. return to the stack process, stop if a high-priority interrupt is received and generate the end chain

　　As can be seen from the above, interrupt priority and interrupt nesting in addition to the arm priority-based optimization, can let the high-priority tasks in the interrupt execution faster, it is the significance of the priority setting.

　　

6.SysTick System Clock Tick experiment (STM32 interrupt entry)