7th talk about SPI and RAM IP cores

Purpose of study:

(1) familiar with SPI interface and its read-write timing;

(2) Review the $READMEMB command and $display command in the Verilog simulation statement;

(3) Mastering the SPI Interface write sequential operation of the hardware language description process (in this case only write timing for example), for the later description of more complex sequential logic circuit lay the foundation.

Learning process:

" SPI relevant knowledge of "

①SPI faster than the serial port, using the source synchronous transmission mode, and for serial transmission, the application scenario is different, timing and interface name will be different;

② serial Flash Read and write erase commands can be communicated through the SPI interface, the CPU chip and FPGA can communicate through the SPI interface, some chip parameter registers can also be configured through the SPI mode;

③spi Interface Description

Figure 1 SPI interface

SCLK: The host gives the slave the system clock signal;

SDI: The host outputs the data signal to the slave machine;

SDO: The output from the machine to the host data signal;

CS: Chip selection signal (active at high level here);

SDIO (three-wire mode): Two-way data bus between host and slave.

" DAC3283 Chip and SPI about the content "

The register mapping for the DAC3283 chip is shown in 1:

Figure 1 Register map for DAC3283 chip

As shown in Figure 1, this DAC chip has a total of 32 registers that need to be configured (CONFIG0~CONFIG31) and each register is 8bit.

"About the configuration of these registers" for a small number of registers, you can directly define a few reg-type variables, and then use these reg variables to initialize the registers to be configured, and for such as this example has so many registers need to be configured, It is necessary to initialize the registers through the ROM or ram of the FPGA, i.e., the configuration parameters are written to the FPGA ROM or RAM, and then the parameters are read out from ROM or RAM by FPGA and written to the registers of the external chip. In this case, it is written to the DAC3283 chip via the SPI interface.

" DAC3283 of the Chip SPI interface Timing "

Figure 2 Write timing diagram for SPI

Fig. 3 reading sequence diagram of SPI

First, a few of the signal names in Figure 2 and Figure 3 are described. The SCLK is a clock signal sent by the FPGA to the DAC chip, and the SDENB is the enable signal of the serial interface (equivalent to the chip selection signal), and the SPI reads and writes only when it is low; for the "three-wire mode" Spi,sdio is a two-way data line, responsible for the data read and write transmission; The Spi,sdio of the four-wire mode is also a bidirectional data cable, but the ALARM_SDO is a read-only data line that is responsible for the transmission of the DAC chip output data only. The data is written to the DAC chip at the rising edge of the SCLK, and is read from the DAC chip at the falling edge of the SCLK.

Then, introduce the data content of each SPI transmission. In this example, the SPI uses a high-level post-low transmission of the serial transmission, each transmission of 16bit, wherein the first 8bit constitutes the SPI instruction cycle, after 8bit constitutes the SPI data cycle. In the first 8bit, RWB (r/w) is read/write control signal, namely: if RWB is high, this instruction is read instruction, if RWB is low, this instruction is write instruction. N1, N0 indicates the number of bytes of data transmitted per frame (in the range of 1~4 bytes, without the preceding instruction byte), A3 ... The A0 is the address of each register of the DAC chip.

" SPI The state machine of the interface

Figure 4 DAC Chip register initialization Operation state Machine (conceptual model)

Idle is the starting state (the default), the work_en is the boot enable signal (active high) from the external input, and wait is the waiting state, in this case, after waiting for 8 clock cycles (wait_cnt[3] = = 1 ' B1) to enter the READ_MEM state (read memory state), Direct reading of data in RAM; Write_reg is a write register state that sends 32 16bit bit-wide data to the DAC chip register in a serial shift, after 1 16bit bits of data have been shifted (shift_cnt = = 4 ' D15 && Pose_flag = = 1 ' B1 && data_end! = 1 ' B1) go back to the wait state, then wait 8 clock cycles, re-execute READ_MEM status and Write_reg state, Until all 32 data have been read and written before entering the stop state (shift_cnt = = 4 ' D15 && pose_flag = = 1 ' b1 && data_end = 1 ' B1), pull up the conf_end signal.

"Design Steps"

(1) Write spi_ctrl.v file, first write the frequency divider counter, the 50MHz system clock is divided into 1MHz as the SPI Clock SPI_CLK (generally 50~60mhz, but here is only a demonstration experiment, with 1MHz), at the same time, produce clk_p and Clk_ N two reg signal with phase opposite, 1MHz frequency, clk_p is a positive phase clock signal to trigger the pulse sign signal Pose_flag (sign the arrival of the rising edge of the SPI Clock signal), the clk_n is the clock signal of the inverting phase, which is used as the SPI_CLK for the SPI as the clock, The above total must write 4 always statement block.

(2) Create a 16bit x 32 single-Port RAM IP core (read-only), and instantiate to SPI_CTRL.V, complete the MIF file editing and copying.

(3) Declaring state machine variables, write state machine (two-segment), including the waiting state of the counter, the address generation module read RAM (a system clock cycle read 1 data), the serial shift register (left shift, move the highest position), shift operation counter, Data_end signal control module, data output module, Chip select Signal Control module, Conf_end signal control module and status Jump module and other parts.

(4) Write testbench files and run.do files, run simulations and analyze simulation results (run 300US). The requirements for the Testbench file are as follows: ① can use the $READMEMB command to read the data in the Dac_ini_16x32.mif file, ② can be used in the REC_SPI task block to achieve the data collection of SPI transmission, and Dac_ini_ Proofread the data in the 16x32.mif file, and then use the $display command to display the proofing results and data information.

"Code Implementation"

(1) Design a counting frequency divider module, using 50MHZ system clock to generate 1MHZ clock signal for SPI read/write operation, and produce clk_p and clk_n two phase opposite, frequency is 1MHz signal:

At the same time, produces a flag clk_p rising along the sign signal Pose_flag, using it to unify the system's global clock:

"Precautions" try not to use the clk_p or Clk_n generated by the crossover as the trigger condition for always blocks! Cause: The clock signal to a large extent determines the performance and reliability of the entire design, should try to avoid the use of FPGA internal logic generated by the clock, because it is easy to lead to function or timing problems, internal logic generated clock signal prone to glitches (poor cabling quality), affect signal quality, while, The inherent delay of combinational logic circuits can also lead to timing problems. For a detailed explanation, see the P59 of the privileged "dive into FPGA" book.

(2) Creation and example of RAM IP cores:

Figure 5 Parameter configuration of RAM IP core

Figure 6 Removing the Q-side register

Figure 7 Creating and adding a MIF file

Figure 8 Checking the sample file

Instantiate to the SPI_CTRL.V file:

(3) Declaring state variables and state parameters, write state machine:

State Jump Control:

① Write state machine write to wait state, found that need to produce wait_end signal, and wait_end signal is generated by counting wait 8 clock cycle, it is necessary to design the wait state Wait count module first:

Then, use the design wait_end signal Generation module:

② Write state machine write to the Read_mem state, the discovery needs to first read the data in RAM, it is necessary to design the module to generate read RAM address:

③ writes the state machine to the Write_reg state, it is discovered that the data read from RAM is cached (via the SHIFT_BUF cache), and then is sent to the DAC chip (the serial shift register) via the SDI line on a per-bit basis:

Then, the design module produces a shift-complete sign signal shift_end:

Then, design the SPI interface data output module, the chip Select Signal control module and the clock signal generation module:

Data is sent to the SPI_SDI interface, each frame transmits 16bit of data, when the transmission of 32 16bit of data, the need to produce a data_end flag signal, flag all data has been transmitted:

When the transmission of 32 16bit of data, is completed the DAC chip 32 register configuration, it is necessary to produce a conf_end flag signal, the completion of the flag configuration operation:

" Testbench and the run.do "

Testbench file:

① uses the file control task $readmemb to read the data from the DAC_INI_16X32.MIF file and initialize the memory Mif_data (reg [15:0] mif_data[0:31]) with this data:

② a task called Spi_check, which recycles the SPI communication data and proofread it with the data in the Dac_ini_16x32.mif file, and if the data is consistent then output the index and specific content of the data, otherwise prompt "SPI write is error!" ：

Run.do file:

"Simulation Results and Analysis"

Figure 9 Information for the Transcript window 1

Figure Transcript Window Information 2

9. Figure 10 shows that the data recovered from the SPI interface is consistent with the data in the MIF file, thus testbench the correctness of the SPI data transfer.

Figure 11 State Machine View

As shown in 12, is the overall picture of the SPI simulation waveform:

Figure 12 Simulation Waveform Figure 1

As shown in 13, the rising edge of the SPI_CLK is aligned to the center of the SPI_SDI data to meet the requirements of the DAC chip SPI write timing, i.e. the data is written to the DAC chip when the clock signal rises along.

Figure 13 Simulation Waveform Figure 2

14 shows the presence of the state machine jumping to the Stop state (10000) and the Data_end rising edge.

Figure 14 Simulation waveform Figure 3

Figure 15 Simulation waveform Figure 4

As shown in Figure 15, in the Write_reg state, the chip selection signal SPI_CSN low state of the duration of about 16us, and the spi_clk period is 1us, so the SPI each shift transmission occupies 16 SPI clock cycles, This is consistent with the idea of transferring 16bit of data per frame designed in the code.

7th talk about SPI and RAM IP cores