80386 Memory Paging mechanism

80386 start to support memory paging management mechanism. The paging mechanism is the 32nd part of the memory management mechanism. The segment management mechanism realizes the transformation of the virtual address (the logical address composed of the segment and the offset) to the linear address, and the paging management mechanism realizes the transformation of the linear address to the physical address. If the paging management mechanism is not enabled, then the linear address is the physical address. This article describes how 80386 of memory paging management mechanisms and linear addresses are converted to physical addresses.

< a > memory paging management mechanism

In protected mode, the highest-bit PG bit in the control register CR0 controls whether the paging management mechanism is in effect. If pg=1, the paging mechanism takes effect, and the linear address is converted to a physical address. If pg=0, the paging mechanism is invalid, the linear address is directly used as the physical address. It is important to note that the paging mechanism may take effect only under protected mode. Only if the PE bit is guaranteed to be 1, it is possible to make the PG bit 1, otherwise it will cause the general protection fault.

The paging mechanism divides the linear address space and the physical address space into blocks of the same size. Such blocks are called pages. The paging mechanism realizes the transformation of the linear address to the physical address through the mapping between the page of the linear address space and the page of the physical address space. The mapping between the pages of the linear address space and the pages of the physical address space can be determined as needed, and can be changed as needed. Any page of the linear address space that can be mapped to any page in the physical address space.

The main purpose of implementing the linear address-to-Physical address translation mapping using the paging management mechanism is to facilitate the realization of virtual memory. Unlike the size of a segment, the size of the page is equal and fixed. According to the logical division of the program, and according to the realization of virtual memory convenient partition page.

In 80386, the size of the page is fixed at 4K bytes, and the boundary address of each page must be a multiple of 4K. Therefore, the 4G size of the address space is divided into 1M pages, the start address of the page has the form of "xxxxx000h". To do this, we refer to the high 20-bit xxxxxh of the page start address as the page number. The number of the linear address space page is the high 20 bits of the page start boundary address, and the page number of the physical address space is the high 20 bits of the physical address at the beginning of the page. Visible, page number left 12 is the beginning of the page address, so the page number is defined pages.

Because the page size is fixed at 4K bytes and the page boundary is a multiple of 4K, the low 12-bit address remains the same during the conversion of a 32-bit linear address to a 32-bit physical address. In other words, the low 12 bits of a linear address are 12 bits lower than the physical address. Assuming that the paging mechanism uses a transformation map to map the Xxxxxh page of a linear address space to the YYYYYH page of the physical address space, the linear address xxxxxxxxh is converted to YYYYYXXXH. Therefore, the transformation of the linear address to the physical address is to resolve the mapping of the page to the physical address space of the linear address space, which is the conversion of the linear address high 20 bits to the physical address high 20 bits.

< two > Linear address-to-physical address conversion

1. MAP table structure

The mapping between the pages of the linear address space and the pages of the physical address space is described with a table. Since the 4G address space is divided into 1M pages, if you use a table to describe this mapping, then the mapping table will have 1M table entries, if each table entry occupies 4 bytes, then the mapping table will occupy 4M bytes. To avoid the mapping table taking up such a large memory resource, the 80386 page mapping table is divided into two levels.

The first level of the page map table, called the page catalog table, is stored in a 4K-byte physical page. The page catalog table has a total of 1K table entries, where each table entry is 4 bytes long and contains the page number of the Physical address space page that corresponds to the second-level table. The second level of the page map table is called the page table, and each page table is also arranged in a 4K-byte page. Each page table has 1K table entries, each of which is 4 bytes long and contains the number of the corresponding physical address space page. Since both the page Catalog table and the page table are made up of 1K table entries, using a 10-bit index allows you to specify the table entry, which means that the physical address of the table entry is obtained by multiplying the 10-bit index value by the 4 base site.

The following illustration shows the structure of a page map table consisting of a page catalog table and a page table. From the diagram, the control register CR3 the specified page catalog table, the page catalog table can specify 1K page tables, which can be scattered in any physical page, without the need for continuous storage; Each page table can specify a page of 1K physical address space, and the pages of those physical address spaces can be arbitrarily dispersed in the physical address space. It is important to note that the base address of the Storage page Catalog table and page table is aligned on the 4K byte boundary.

2. Table Item Format

The table entries in both the page Catalog table and the page table are in the format shown in the following figure. As seen from the figure, the highest 20 bits (bit 12-bit 31) contain the page numbers of the physical address space pages, which is the high 20 bits of the physical address. The low 12-bit property that contains the page. The bits in the properties shown in the following image are 0 bits that are reserved by Intel Corporation for processors such as 80486, and must be set to 0 for 80386 programming. The AVL field in bits 9 to 11 is for software use. The lowest bit of the table entry is the existence of the attribute bit, which is recorded as P. The P-bit indicates whether the table entry is valid. The P=1 table entry is valid, the P=0 table entry is invalid, and the rest of the table entries are available to the software, and 80386 does not explain any of the other bits in the P=0 table entry. During a linear address-to-physical address conversion through a page catalog table and a page table, a page failure occurs regardless of whether an invalid table entry is encountered in the page catalog table or in the page table. The effect of other attribute bits is described below.

Page Catalog table or page

Table entry format bit31-bit12 bit11-bit9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 physical page number AVL 0 0 D A 0 0 u/s r/w P

3. Conversion of linear address to physical address

The paging management mechanism implements the conversion of 32-bit linear addresses to 32-bit physical addresses through the above page catalog tables and page tables. The high 20 bits of the control register CR3 are the page numbers of the physical pages where the pages catalog table resides. First, the highest 10 bits of the linear address (22 to 31) as the index of the page catalog table, the corresponding table entry contains the page number specified in the table, and then the linear address of the middle 10 bits (ascended to 12 to 21) as the specified page table entries in the table index, The corresponding table entry contains a page number that specifies one of the physical address spaces, and finally, the page number of the specified physical page is 20 bits high, and the low 12 bits of the linear address are not changed to the low 12 bits of the 32-bit physical address.

To avoid accessing the in-memory page table every time the memory is accessed, the 80386 processor's hardware stores the most recently used linear-Physical address translation functions in the page conversion cache inside the processor. The cache is always consulted before accessing the memory page table, and the Level two page table in memory is accessed only if the required conversion is not in the cache. The page conversion cache is also known as the page transformation lookup cache, which is recorded as a TLB.

In the paging mechanism, the correlation between the data in the cache and the data in the page table is not maintained by the 80386 processor, but must be kept by the operating system software, that is, the processor does not know when the software will modify the page table, in a reasonable system, the page table can only be modified by the operating system, The operating system can ensure correlation by refreshing the cache directly after the software modifies the page table. The cache refresh is done by loading the processor control register CR3, and the actual process may be implemented with the following two instructions:

MOV EAX,CR3

MOV cr3,eax

A special case of an important modification to a page table entry does not require a page conversion cache refresh, which is the case of modifying any part of a table entry that does not exist, even if the P-bit itself is changed from P=0 to p=1, because invalid table entries are not stored in the cache. Therefore, you do not need to flush the cache when invalid table entries are changed. This means that you do not have to flush the cache when a page is read from disk to make it exist.

In a multiprocessor system, particular attention must be paid to whether a program executed in one processor alters a page table that may be accessed concurrently by another processor. In the 80386 processor, a multiprocessor configuration is supported by using non-divided read/modify/write cycles whenever the page table entry is to be updated and the D-bit and a-bit are set. Software updates for page table entries require the use of the lock prefix to ensure that the instructions to modify the page table work in an unreadable read/modify/write cycle. Before changing a page table that may be used by another processor, it is best to use a locked and instruction to clear the P-bit to 0 in an irreducible operation, and then the table entry can be modified as required and then the P position is 1 to make the table entry available. When you modify a page table entry, you must promptly notify (usually using an interrupt mode) that all processors in the system that have been cached by the table item are flushed to the respective page conversion cache to undo the old copy of the table item. Before the old copy of the table item is refreshed, the processors can continue to access the old page and can set the D-bit of the table entry that is being modified. If this causes the table item modification to fail, the paging mechanism cache is best done after it has been marked as not present and refreshed before additional modifications are made to the table entry.

4. Non-existent page table

Using the above page mapping table structure, storing all 1K page tables requires 4M bytes, in addition to 4K bytes to store the page catalog table. Such a two-level page mapping table appears to occupy 4K more bytes than a single full page mapping table. In fact, there is no need to store the full level Two page mapping table in memory. A page table is not required in a two-level page map structure for parts that do not exist or are not used in a linear address space. In addition to assigning a physical page to a page catalog table, the page map table size corresponds to the actual linear address space size that is used only if the page table is assigned a physical page when needed. Because any actual running program uses a linear address space that is much smaller than 4G bytes, the physical page used to assign to the page table is also much smaller than 4M bytes.

The presence bit p in the page Catalog table entry indicates whether the corresponding page table is valid. If the p=1 indicates that the corresponding page table is valid, it can be used for address translation, if p=0 indicates that the corresponding page table is invalid. If you attempt to convert a linear address to a physical address through an invalid page table, the page failure will be caused. Therefore, the attribute bit p in the Page Catalog table entry allows the operating system to simply allocate a physical page to a page table that overrides the linear address range that is actually used.

The property bit P page in the page Catalog table entry can be used to store the page table in virtual storage. When a page failure occurs due to an invalid page table, the page fault handler then requests the physical page, reads the corresponding page table from the disk, and puts the P position in the corresponding page directory table 1. In other words, you can assign a physical page to the page table you want when you need it. This minimizes the number of physical pages that the page table occupies.

5. Sharing of pages

Visible from the above page map table structure, the paging mechanism does not have global page and local page provisions. Each task can use its own page mapping table to implement the transformation of linear address to physical address independently. However, if the page mapping table used by each task has some of the same mappings, then partial-page sharing can be implemented.

The common method of implementing page sharing is to share the linear address space, that is, the same mapping information for the same linear address space of the different tasks, which is the same as the partial page table or the page number of some table items in the table. For example, if task A and task B are using the same page table of Contents table A and page No. 0 in table B, which is the same as page 0, then the 00000000H to 003FFFFFH linear address space for task A and task B maps to the same physical page. For example, task A and task B use a different page table 0, but the page numbers for items No. 0 through 0FFH in the two pages correspond to the same, then the 00000000H to 000FFFFFH linear address space for task A and task B maps to the same physical page.

It is important to note that shared page tables are best specified by the same catalog entries in the two-page directory. This is important because it guarantees that the same linear address range will be mapped to the global zone in both tasks.

< three > page-level protection and virtual memory support

1. Page-level protection

80386 provides not only segment-level protection, but also page-level protection. The paging mechanism distinguishes between only two privileged levels. Privileged levels 0, 1, and 2 are collectively referred to as system privilege levels, and privilege level 3 is called user privilege level. The protection attribute bits r/w and u/s in the table entries for the page catalog tables and page tables shown in the figure above are used to protect the page.

The bit 1 of the table entry is the read-write attribute bit, which is recorded as r/w. The R/W bit indicates whether the page specified by the table entry is readable, writable, or executed. If r/w=1, the page specified by the table entry can be read, write, or execute, and if r/w=0, the page specified for the table entry is readable or executed, but cannot be written to the specified page. However, r/w bit-to-page write protection only works when the processor is at the user privilege level, and when the processor is at the system privilege level, the R/W bit is ignored, which can always be read, written, or executed.

The bit 2 of the table entry is the user/system attribute bit, which is recorded as u/s. The U/S bit indicates whether the page specified by the table entry is a user-level page. If U/s=1, the page specified by the table entry is a user-level page that can be accessed by a program executed under any privileged level, and if u/s=0, the page specified by the table entry is a system-level page that can only be accessed by a program executed under the system privilege level. The following table lists the permissions that user-level programs and system-level programs have on user-level and system-level pages, respectively, under page-level protection determined by the above-mentioned attribute bits r/w and u/s.

Page-level

Protection

Property u/s r/w User-level access permissions system-level access 0 0 No read/write/execute 0 1 No read/write/execute 1 0 read/execute read/write/execute 1 1 Read/write/execute read/write/execute

As seen in the table above, user-level pages can be defined as read/write/execute only and are allowed for reading/writing. System-level pages are always readable/write/execute for system-level programs, and are always inaccessible to user-level programs. As with the staging mechanism, programs executed at the outer user level can access only user-level pages, while the inner-tier system-level programs can access both system-level pages and user-level pages. Unlike the fragmentation mechanism, programs executed at the system level of the inner tier have read/write/execute access to any page, even if the user page is specified to allow only read/execute, and the internal system level program has write access to the page.

The protection attribute bits r/w and u/s in the page catalog table entries protect all 1K pages specified by the table entry specified by the page table. Therefore, the values of the protected property bits r/w and u/s that are referenced when the page is accessed are calculated by combining the values of the protected property bits in the page Catalog table entry and the page table entry. The following table lists the values of the protected attribute bits before and after the combined calculation, and the combined calculation is the "and" operation.

of the combined page

Protection > Properties Catalog Table Entry u/s Page table entry u/s combination u/s Catalog table Item r/w page table Item r/w combination r/w 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 1 1

As in the 80386 address translation mechanism, page-level protection, which is supported by the paging mechanism, also functions after the segment-level protection supported by the staging mechanism, just as the paging mechanism works after the fragmentation mechanism. Test the section-level protection first, and if you enable paging, then test page-level protection after the check passes. If the type of the segment is read/write, and the page is specified to allow only read/execute, then no write is allowed, and if the type of the segment is read-only/execute, then no write is allowed, regardless of page protection.

Page-level protection checks are performed during the translation of a linear address into a physical address, and if a page is accessed (read/write/execute) in violation of the provisions of the page Protection property, the page exception is raised.

2. Support for virtual storage

The P-bit in the page table entry is the key to supporting virtual memory with paging mechanism. P=1, which indicates that the page specified by the table entry exists in physical memory, and that the high 20 bits of the table entry are the page numbers of the physical page; p=0, the pages in the linear address space that correspond to the physical addresses in the sky are not in the physical memory. If a program accesses a page that does not exist, it causes a page exception, so that the operating system can read the nonexistent page from disk, fill in the corresponding table entry with the page number of the physical page, and place the P position in the table entry at 1, and then restore the program that caused the exception to run.

In addition, access bits A and write flag bits d in the table entries are also used to support the efficient implementation of virtual storage.

The bit 5 of the table entry is the access attribute bit, which is recorded as a. During the conversion of a linear address to a physical address in order to access a storage unit, the processor always puts the corresponding table entry in the page catalog table and a position 1 in the corresponding table entry in its specified page table, unless the page table or page does not exist, or access violates the protection property provisions. Therefore, a=1 indicates that the corresponding physical page has been accessed. The processor never clears a bit. By periodically detecting and clearing the A-bit, the operating system can determine which pages have not been accessed in the most recent time. When memory resources are scarce, these recently inaccessible pages are likely to be selected, swapping them out of memory to disk.

The bit 6 of the table entry is the write flag bit, which is recorded as D. In order to access a storage unit and a linear address to the physical address of the conversion process, if it is write access and can write access, the processor will be in the page table in the corresponding table key in the D position 1, but does not put the page directory table in the corresponding table key in the D 1. When a page is read into memory from disk, the D-bit of the corresponding table entry in the page table is cleared by 0. Therefore, d=1 indicates that the corresponding physical page has been written. When a page needs to be swapped out from memory to disk, if the D bit of the page is 1, then a write operation is required (the processor does not clear the D-bit of the corresponding page table entry when writing the in-memory page to disk). However, if the D bit of a page to be written to disk is 0, then the actual disk write operation is not required, as long as you simply discard the page in memory. Because the pages in memory have exactly the same content as the pages on the disk.

< four > Page exception

When the paging mechanism is enabled, the linear address is no longer directly equal to the physical address, and the linear address is transformed by a paging mechanism to become the physical address. During the conversion process, a page exception is caused if one of the following conditions occurs:

(1) A p=0 in a table item or a table entry within a page table that involves a page in a table of contents, that is, the page is not in memory;

(2) Access to the page was found to attempt to violate the page protection properties.

The interrupt vector number for the report page exception is (0EH). The page exception belongs to the fault class exception. When entering the fault handler, the saved instruction Pointer CS and the EIP point to the failed instruction. Once the cause of the page failure is excluded, a iret instruction can be passed from the page fault handler to directly re-execute the failed instruction.

When a page failure occurs, the processor loads the linear address that caused the page fault into CR2. The page fault handler can use this linear address to determine the corresponding page Catalog entry and page table entry.

Page faults also provide an error code in the stack, with the format of the error code as shown in the following figure. Where U-bit represents the privileged level that causes the failure program, u=1 represents the user privilege level (Privilege Level 3), u=0 represents the system privilege level (privilege level 0, 1, or 2), the W bit represents the access type, w=0 represents read/execute, W=1 is write, the P-bit represents the exception type, and P=0 indicates that the page does not exist 1 indicates a protection failure. The response processing mode for page faults is the same as for other failures.

Error code

Format bit15-bit3 BIT2 BIT1 BIT0 not using U W P

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