80386 of the exception type

As interrupts are divided into multiple types, exceptions can be divided into multiple types.

1.80386 identified exceptions

80386 different categories of exceptions identified and given the corresponding interrupt vector number as shown in the table below. Some exceptions also provide some additional information in the form of an error code passed to the exception handler, "None" in the Error code column indicates no error code, "Yes" indicates an error code. -->
-->

Different Often One Overview Table	Vector number	Exception name	Exception type	Error code	Related directives
0	Division Error	Fault	No	Div,idiv
1	Debug exceptions	Fault/Trap	No	Any instruction
3	Single byte INT3	Trap	No	INT 3
4	Overflow	Trap	No	Into
5	Boundary check	Fault	No	Bount
6	Illegal operation code	Fault	No	Illegal instruction encoding or operand
7	Device Not available	Fault	No	Floating point instruction or wait
8	Double fault	Stop	Yes	Any instruction
9	Coprocessor segment out of bounds	Stop	No	Floating point instructions for accessing storage
0AH	Invalid TSS exception	Fault	Yes	JMP, call, Iret, or interrupt
0BH	Segment does not exist	Fault	Yes	Instructions for loading segment registers
0CH	Stack Segment exception	Fault	Yes	Any instruction that loads the SS register, any instructions that are accessed by the SS-addressed segment
0DH	Generic Protection exception	Fault	Yes	Any privileged instructions, any instructions to access the memory
0EH	Page exception	Fault	Yes	Any instructions to access the memory
10H	Co-processor Error	Fault	No	Floating point instruction or wait
11h-0ffh	Soft interrupt	Trap	No	INT N

-->

As the above table shows, some of the interrupt vector numbers in protected mode conflict with the real mode interrupt vector number. Distribution of interrupt vector number in real mode based on PC microcomputer System 8086/8088 CPU, the interrupt vector number in the table above is allocated in 80386. In fact, Intel retains these conflicting interrupt vector numbers when announcing 8086/8088. In spite of this conflict, however, the microprocessor system with 80386 CPU can still maintain the compatibility with the microcomputer system with 8086/8088 CPU, because in 80386 real mode, there is hardly any exception that interrupts vector number and interrupt vector number that are supplied when interrupt request of external hardware. It should be noted that in protected mode the 8259A Interrupt controller must be reset to produce a hardware interrupt vector that does not conflict with the exception.

2. Fault class exception

When a failure occurs, the control is transferred to the fault handler, and the value of the saved breakpoint Cs and Eip points to the instruction causing the failure to resume execution after troubleshooting.

(1) Division error failure (Exception 0)

Division error is a failure. When the div instruction or idiv instruction is executed, if the divisor equals 0 or the quotient is too large to hold the operator's operand, the failure occurs. Division failure does not provide an error code.

(2) Boundary check Failure (Exception 5)

If the bound instruction finds that the value being tested exceeds the range given in the instruction, a boundary check failure occurs. Boundary check failure does not provide an error code.

(3) Illegal operation code failure (abnormal 6)

If 80386 cannot identify the bit pattern of the CS and EIP points to the storage unit as part of an instruction, an illegal opcode failure occurs. Such a failure occurs when: (1) The contents of the opcode field are not a legitimate 80386 instruction code, (2) a register operand is used when the memory operand is required, and (3) a lock prefix is used before an instruction that cannot be locked. Illegal operation code failure does not provide opcode.

(4) Equipment unavailable failure (abnormal 7)

The device is not available to support 80387 digital coprocessor. In systems that do not have 80387 coprocessor hardware, the handler for this exception can be substituted for the coprocessor's software emulator. When a task switch occurs, a 80387 register state switch is made only when a new task uses a floating-point directive. The device is not available for failure to provide an error code. The fault occurs in the following cases: (1) when executing a floating-point instruction, the EM bit or TS bit in the control register CR0 is 1, (2) The TS and EM bits in the control register CR0 are 1 when executing the wait instruction. It is important to note that the handler for this exception must be a process and not a task, or the TS bit will be set 80386 when the handler publishes a iret instruction. The coprocessor then executes the failed instruction again and finds that the TS is set, so that the exception 7 occurs again, resulting in an endless loop. The handler can be invoked through the trap door, because interrupts can be allowed during execution.

(5) Invalid TSS failure (abnormal 0AH)

When the selection is being loaded from the Task State section TSS, an invalid TSS failure occurs if a segment exception occurs that does not have a fault.     When entering the fault handler, the saved CS and Eip point to the failed instruction, or the fault points to the first instruction of the task when it occurs as part of a task switch. Invalid TSS failure provides an error code, the format of the error code as shown in the following figure. The selection of the sub section is a selection of TSS that points to the failure. The main component of the 16-bit error code is the selector, pointing to the TSS selector that caused the failure. The high 13-bit is the index part of the selector, and the TI bit is the description of the indicator bit. -->
-->

Format of the error code
Bit15-bit3	BIT2	BIT1	BIT0
Select the index portion of the child	TI	IDT	EXT

-->
-->The error code format shown above is the general format of the error code for an exception. It is visible from the diagram that the error code does not contain the RPL of the selector and is replaced by the IDT bit and the ext bit. When handling an exception or an external interrupt, an exception occurred, then ext position 1. When a table entry is read from the interrupt descriptor IDT and an exception is generated, IDT position 1, which occurs only during an interrupt or exception processing.     When there is no selection of the child, the component of the error code select the sub part of the value is 0. Some of the reasons for invalid TSS failures are as follows: The segment limit length in the TSS descriptor is less than 103, the invalid LDT descriptor, or the LDT does not appear; The stack segment is not a writable segment; the stack segment selects the descriptor of the sub index beyond the descriptor chart boundary; stack segment DPL with the new CPL mismatch; the rpl of the stack segment selector is not equal to CPL; The descriptor for the code snippet to select the child is outside the descriptor chart bounds; The code snippet selector does not point to the code snippet; The DPL of the inconsistent code segment is not equal to the new Cpl; the DPL of the consistent code segment is greater than the The selection of DS, ES, FS or GS points to an unreadable segment (such as a system segment); The descriptor for the DS, ES, FS, or GS is beyond the bounds of the descriptor chart.

(6) section does not have a failure (abnormal 0BH)

When the processor loads a descriptor into a high speed buffer of a non-SS segment register, if it finds other aspects of the descriptor valid, and the P bit is 0 (indicating that the corresponding segment does not exist), the segment does not fail when the descriptor is referenced. The case of the SS segment is included in the stack segment failure.     When entering the fault handler, the saved CS and EIP perform the instructions of the failure, or the first instruction of the task when the fault occurs as part of a task switch. section does not have a failure provides an error code that contains the segment selector that caused the failure. The error code is formatted as shown in the previous illustration. Select the index in which the sub-index section is the segment descriptor that causes the segment to not fail.